Issued Patents All Time
Showing 26–50 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10218580 | Generating physically aware network-on-chip design from a physical system-on-chip specification | Rajesh Chopra, Yang Lin | 2019-02-26 |
| 10218581 | Generation of network-on-chip layout based on user specified topological constraints | Pier Giorgio Raponi, Eric Norige | 2019-02-26 |
| 10110499 | QoS in a system with end-to-end flow control and QoS aware buffer allocation | — | 2018-10-23 |
| 10084692 | Streaming bridge design with host interfaces and network on chip (NoC) layers | Rajesh Chopra | 2018-09-25 |
| 10084725 | Extracting features from a NoC for machine learning construction | Pier Giorgio Raponi, Nishant Rao | 2018-09-25 |
| 10074053 | Clock gating for system-on-chip elements | Sandip Das, Poonacha Kongetira | 2018-09-11 |
| 10063496 | Buffer sizing of a NoC through machine learning | Eric Norige, Nishant Rao | 2018-08-28 |
| 10050843 | Generation of network-on-chip layout based on user specified topological constraints | Pier Giorgio Raponi, Eric Norige | 2018-08-14 |
| 10042404 | Automatic generation of power management sequence in a SoC or NoC | Anup Gangwar, Vishnu Mohan Pusuluri, Poonacha Kongetira | 2018-08-07 |
| 10027433 | Multiple clock domains in NoC | Joji Philip, Joseph B. Rowlands | 2018-07-17 |
| 9928204 | Transaction expansion for NoC simulation and NoC design | Eric Norige | 2018-03-27 |
| 9864728 | Automatic generation of physically aware aggregation/distribution networks | Eric Norige | 2018-01-09 |
| 9860197 | Automatic buffer sizing for optimal network-on-chip design | — | 2018-01-02 |
| 9830265 | Reuse of directory entries for holding state information through use of multiple formats | Joe Rowlands | 2017-11-28 |
| 9829962 | Hardware and software enabled implementation of power profile management instructions in system on chip | Rimu Kaushal, Anup Gangwar, Vishnu Mohan Pusuluri | 2017-11-28 |
| 9825809 | Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip | Joji Philip | 2017-11-21 |
| 9825887 | Automatic buffer sizing for optimal network-on-chip design | — | 2017-11-21 |
| 9785732 | Verification low power collateral generation | Vishnu Mohan Pusuluri, Santhosh Patchamatla, Rimu Kaushal, Anup Gangwar | 2017-10-10 |
| 9781043 | Identification of internal dependencies within system components for evaluating potential protocol level deadlocks | Eric Norige, Joji Philip, Joseph B. Rowlands | 2017-10-03 |
| 9774498 | Hierarchical asymmetric mesh with virtual routers | Eric Norige, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra, Joseph B. Rowlands | 2017-09-26 |
| 9769077 | QoS in a system with end-to-end flow control and QoS aware buffer allocation | — | 2017-09-19 |
| 9762474 | Systems and methods for selecting a router to connect a bridge in the network on chip (NoC) | Eric Norige, Pier Giorgio Raponi | 2017-09-12 |
| 9742630 | Configurable router for a network on chip (NoC) | Joji Philip | 2017-08-22 |
| 9699079 | Streaming bridge design with host interfaces and network on chip (NoC) layers | Rajesh Chopra | 2017-07-04 |
| 9660942 | Automatic buffer sizing for optimal network-on-chip design | — | 2017-05-23 |