Issued Patents All Time
Showing 51–75 of 149 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7422952 | Method of forming a BJT with ESD self protection | Peter J. Hopper, Yuri Mirgorodski | 2008-09-09 |
| 7411251 | Self protecting NLDMOS, DMOS and extended voltage NMOS devices | — | 2008-08-12 |
| 7394133 | Dual direction ESD clamp based on snapback NMOS cell with embedded SCR | Peter J. Hopper, Philipp Lindorfer | 2008-07-01 |
| 7387918 | Method of forming a silicon controlled rectifier structure with improved punch through resistance | Peter J. Hopper, Ann Concannon, Marcel Ter Beek | 2008-06-17 |
| 7379283 | ESD protection circuit with a low snapback voltage that is protected from fast non-ESD voltage spikes and ripples | Douglas Robert Farrenkopf | 2008-05-27 |
| 7375393 | Non-volatile memory (NVM) retention improvement utilizing protective electrical shield | Yuri Mirgorodski, Peter J. Hopper | 2008-05-20 |
| 7375579 | Programming of fuse-based memories using snapback devices | Peter J. Hopper, Philipp Lindorfer | 2008-05-20 |
| 7339835 | Non-volatile memory structure and erase method with floating gate voltage control | Yuri Mirgorodski, Peter J. Hopper | 2008-03-04 |
| 7298599 | Multistage snapback ESD protection network | Peter J. Hopper, Yuri Mirgorodski, Philip Lindorpher | 2007-11-20 |
| 7298653 | Reducing cross die variability in an EEPROM array | Peter J. Hopper, Philipp Lindorfer, Yuri Mirgorodski | 2007-11-20 |
| 7285805 | Low reference voltage ESD protection device | Peter J. Hopper | 2007-10-23 |
| 7268398 | ESD protection cell with active pwell resistance control | Ann Concannon, Peter J. Hopper | 2007-09-11 |
| 7259411 | Vertical MOS transistor | Peter J. Hopper, Yuri Mirgorodski, Peter Johnson | 2007-08-21 |
| 7238553 | Method of forming a high-voltage silicon controlled rectifier structure with improved punch through resistance | Andy Strachan, Peter J. Hopper, Philipp Lindorfer | 2007-07-03 |
| 7221608 | Single NMOS device memory cell and array | Peter J. Hopper, Philipp Lindorfer | 2007-05-22 |
| 7221036 | BJT with ESD self protection | Peter J. Hopper, Yuri Mirgorodski | 2007-05-22 |
| 7218555 | Imaging cell that has a long integration period and method of operating the imaging cell | Peter J. Hopper, Philipp Lindorfer, Robert Drury | 2007-05-15 |
| 7217966 | Self-protecting transistor array | Peter J. Hopper, Philipp Lindorfer | 2007-05-15 |
| 7209503 | Laser powered integrated circuit | Peter J. Hopper, Philipp Lindorfer, Yuri Mirgorodski | 2007-04-24 |
| 7202538 | Ultra low leakage MOSFET transistor | Peter J. Hopper, Philipp Lindorfer, Robert Drury | 2007-04-10 |
| 7196361 | Cascoded bi-directional high voltage ESD protection structure | Willem Johannes Kindt, Peter J. Hopper | 2007-03-27 |
| 7192853 | Method of improving the breakdown voltage of a diffused semiconductor junction | Andrew Strachan | 2007-03-20 |
| 7192857 | Method of forming a semiconductor structure with non-uniform metal widths | Peter J. Hopper, Philipp Lindorfer, Andy Strachan | 2007-03-20 |
| 7193251 | ESD protection cluster and method of providing multi-port ESD protection | Ann Concannon, Peter J. Hopper, Marcel ter Beek | 2007-03-20 |
| 7180133 | Method and structure for addressing hot carrier degradation in high voltage devices | Peter J. Hopper, Yuri Mirgorodski, Philipp Lindorfer | 2007-02-20 |