Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9515555 | Floating power converter having multiple voltage inputs | — | 2016-12-06 |
| 7379283 | ESD protection circuit with a low snapback voltage that is protected from fast non-ESD voltage spikes and ripples | Vladislav Vashchenko | 2008-05-27 |
| 7339410 | Method and system for providing startup delay | — | 2008-03-04 |
| 6952333 | ESD protection circuit for high-voltage, high DV/DT pads | — | 2005-10-04 |
| 6714067 | Bootstrap capacitor low voltage prevention circuit | — | 2004-03-30 |
| 6515460 | Multiphase switching regulator control architecture for low on time systems that enforces current sharing | — | 2003-02-04 |
| 6229293 | DC-to-DC converter with current mode switching controller that produces ramped voltage with adjustable effective ramp rate | — | 2001-05-08 |
| 6169433 | Method and apparatus using feedback to generate a ramped voltage with controlled maximum amplitude | — | 2001-01-02 |
| 6111440 | Circuit for generating interleaved ramped voltage signals having uniform, controlled maximum amplitude | Jayendar Rajagopalan, Christopher T. Falvey | 2000-08-29 |
| 6100677 | Switching controller chip with internal but not external soft start circuitry and DC to DC converter including such a controller chip | — | 2000-08-08 |
| 6094039 | Switching controller chip operable in selected ones of multiple power switch setting modes | — | 2000-07-25 |
| 5899714 | Fabrication of semiconductor structure having two levels of buried regions | Richard B. Merrill, Samar K. Saha, Kevin E. Brehmer, Kamesh V. Gadepally, Philip John Cacharelis | 1999-05-04 |
| 5889315 | Semiconductor structure having two levels of buried regions | Richard B. Merrill, Samar K. Saha, Kevin E. Brehmer, Kamesh V. Gadepally, Philip John Cacharelis | 1999-03-30 |
| 5854099 | DMOS process module applicable to an E.sup.2 CMOS core process | — | 1998-12-29 |