KW

Kevin Weaver

NS National Semiconductor: 15 patents #97 of 2,238Top 5%
Lsi Logic: 4 patents #471 of 1,957Top 25%
Overall (All Time): #225,391 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7848562 Method of reducing the time required to perform a passive voltage contrast test Steven Jacobson, Duc Huu Nguyen, William Ng, Zachary Joshua Gemmill, Usharani Bhimavarapu 2010-12-07
7470553 Built-in design edit structures Zachary Joshua Gemmill 2008-12-30
7352001 Method of editing a semiconductor die Henry Acedo, Lakshmi Durbha 2008-04-01
7279343 De-packaging process for small outline transistor packages Hiep V. Nguyen, Henry Acedo 2007-10-09
7250310 Process for forming and analyzing stacked die Chetan Paydenkar 2007-07-31
7172977 Method for non-destructive removal of cured epoxy from wafer backside David Zakharian 2007-02-06
7087927 Semiconductor die with an editing structure Henry Acedo, Lakshmi Durbha 2006-08-08
6952106 E-beam voltage potential circuit performance library William Ng, Zachary Joshua Gemmill 2005-10-04
6937351 Non-destructive method of measuring the thickness of a semiconductor wafer Zachary Joshua Gemmill, Steven Jacobson 2005-08-30
6842021 System and method for detecting location of a defective electrical connection within an integrated circuit Gengying Gao 2005-01-11
6801046 Method of testing the electrostatic discharge performance of an IC device Gengying Gao, Mohan Yegnashankaran, Hengyang (James) Lin 2004-10-05
6518074 Backside IC device preparation process Hiep V. Nguyen, Henry Acedo, Smith J. Johnson 2003-02-11
6424167 Vibration resistant test module for use with semiconductor device test apparatus Gengying Gao 2002-07-23
6411111 Electron-electro-optical debug system E2ODS Geng Ying Gao 2002-06-25
6117352 Removal of a heat spreader from an integrated circuit package to permit testing of the integrated circuit and other elements of the package Steve Scott 2000-09-12
6100590 Low capacitance multilevel metal interconnect structure and method of manufacture Visvamohan Yegnashankaran, Hengyang James Lin 2000-08-08
6083848 Removing solder from integrated circuits for failure analysis Emery Sugasawara, Jay Sherman Hidy 2000-07-04
6068727 Apparatus and method for separating a stiffener member from a flip chip integrated circuit package substrate Zhaomin Ji 2000-05-30
6043100 Chip on tape die reframe process Terry Lynne Barrette 2000-03-28
5990543 Reframed chip-on-tape die Terry Lynne Barrette 1999-11-23