Issued Patents All Time
Showing 26–50 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6777920 | Internal power-supply potential generating circuit | Takeshi Hamamoto, Susumu Tanida | 2004-08-17 |
| 6753720 | Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor | Takashi Kono, Katsuyoshi Mitsui | 2004-06-22 |
| 6717887 | Semiconductor memory device having configuration for selecting desired delay locked loop clock | Takashi Kono | 2004-04-06 |
| 6552939 | Semiconductor memory device having disturb test circuit | Takeo Miki | 2003-04-22 |
| 6551846 | Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration | Mikio Asakura, Tetsuo Katoh | 2003-04-22 |
| 6542422 | Semiconductor memory device performing high speed coincidence comparison operation with defective memory cell address | Takeshi Hamamoto, Takashi Kubo | 2003-04-01 |
| 6492863 | Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor | Takashi Kono, Katsuyoshi Mitsui | 2002-12-10 |
| 6490221 | Semiconductor memory device with low power consumption | Mikio Asakura | 2002-12-03 |
| 6477109 | Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein | Yasuhiro Konishi | 2002-11-05 |
| 6477105 | Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver | Kengo Aritomi, Mikio Asakura, Takashi Ito | 2002-11-05 |
| 6417715 | Clock generation circuit generating internal clock of small variation in phase difference from external clock, and semiconductor memory device including such clock generation circuit | Takeshi Hamamoto | 2002-07-09 |
| 6407942 | Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver | Kengo Aritomi, Mikio Asakura, Takashi Ito | 2002-06-18 |
| 6400621 | Semiconductor memory device and method of checking same for defect | Hideto Hidaka, Mikio Asakura, Tetsuo Kato | 2002-06-04 |
| 6341089 | Semiconductor memory device allowing effective detection of leak failure | Seiji Sawada, Mikio Asakura | 2002-01-22 |
| 6301163 | Semiconductor memory device and method of checking same for defect | Hideto Hidaka, Mikio Asakura, Tetsuo Kato | 2001-10-09 |
| 6297624 | Semiconductor device having an internal voltage generating circuit | Katsuyoshi Mitsui, Takashi Kono | 2001-10-02 |
| 6292429 | Synchronous semiconductor memory device allowing data to be satisfactorily rewritten therein | Yasuhiro Konishi | 2001-09-18 |
| 6288957 | Semiconductor memory device having test mode and method for testing semiconductor therewith | Tetsuo Katoh, Mitsutomi Yamashita | 2001-09-11 |
| 6262931 | Semiconductor memory device having voltage down convertor reducing current consumption | Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui | 2001-07-17 |
| 6201437 | Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor | Takashi Kono, Katsuyoshi Mitsui | 2001-03-13 |
| 6195298 | Semiconductor integrated circuit capable of rapidly rewriting data into memory cells | Katsuyoshi Mitsui | 2001-02-27 |
| RE36932 | Semiconductor memory device operating stably under low power supply voltage with low power consumption | — | 2000-10-31 |
| 6111805 | Power-on-reset circuit for generating a reset signal to reset a DRAM | — | 2000-08-29 |
| 6091651 | Semiconductor memory device with improved test efficiency | Takeshi Hamamoto, Shigeru Kikuda | 2000-07-18 |
| 6091648 | Voltage generating circuit for semiconductor integrated circuit device | Katsuyoshi Mitsui | 2000-07-18 |