Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5365474 | Semiconductor memory device | — | 1994-11-15 |
| 5323049 | Semiconductor device with an interconnection layer on surface having a step portion | — | 1994-06-21 |
| 5309023 | Contact structure for interconnection in semiconductor devices and manufacturing method thereof | Katumi Suizu | 1994-05-03 |
| 5280444 | Dram comprising stacked-type capacitor having vertically protruding part and method of manufacturing the same | Yoshinori Okumura | 1994-01-18 |
| 5240872 | Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions | Natsuo Ajika, Atsushi Hachisuka, Yoshinori Okumura, Yasushi Matsui | 1993-08-31 |
| 5241212 | Semiconductor device having a redundant circuit portion and a manufacturing method of the same | Masao Nagatomo | 1993-08-31 |
| 5229314 | Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation | Tomonori Okudaira, Hideaki Arima, Makoto Ohi, Yasushi Matsui | 1993-07-20 |
| 5218219 | Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region | Natsuo Ajika, Hideaki Arima, Atsushi Hachisuka, Tomonori Okudaira | 1993-06-08 |
| 5185284 | Method of making a semiconductor memory device | — | 1993-02-09 |
| 5173752 | Semiconductor device having interconnection layer contacting source/drain regions | Natsuo Ajika, Atsushi Hachisuka, Yoshinori Okumura, Yasushi Matsui | 1992-12-22 |
| 5157469 | Field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulators | Tomonori Okudaira, Hideaki Arima, Makoto Ohi, Yasushi Matsui | 1992-10-20 |
| 5089868 | Semiconductor memory device with improved groove capacitor | — | 1992-02-18 |