Issued Patents All Time
Showing 101–125 of 140 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5208474 | Input circuit of a semiconductor device | Tadato Yamagata, Michihiro Yamada | 1993-05-04 |
| 5204837 | Semiconductor memory device having test mode | Makoto Suwa | 1993-04-20 |
| 5172757 | Method for removing soot by scattering steel balls in a heat-exchanger and heat-exchanger provided with a steel ball scatterer | Masami Kato, Tadashi Tanaka, Satoshi Nakamura, Tsuneo Higashi, Hiroshi Fujiike +1 more | 1992-12-22 |
| 5157630 | Semiconductor memory which can be prevented from shifting to undesired operation mode | Makoto Suwa | 1992-10-20 |
| 5148857 | Method for removing soot by scattering steel balls in a heat-exchanger and heat-exchanger provided with a steel ball scatterer | Masami Kato, Tadashi Tanaka, Satoshi Nakamura, Tsuneo Higashi, Hiroshi Fujike +1 more | 1992-09-22 |
| 5116702 | Electrophotographic light-sensitive material comprising a charge generating layer and a charge transfer layer | Sadao Okano, Kazuya Hongo, Hidekazu Aonuma | 1992-05-26 |
| 5111078 | Input circuit for logic circuit having node and operating method therefor | Kazutoshi Hirayama | 1992-05-05 |
| 5111433 | Semiconductor memory device with inhibiting test mode cancellation and operating method thereof | — | 1992-05-05 |
| 5079743 | Circuit for applying selected voltages to dynamic random access memory | Makoto Suwa, Shigeru Mori | 1992-01-07 |
| 5073874 | Method of and apparatus for reducing current of semiconductor memory device | Michihiro Yamada | 1991-12-17 |
| 5063313 | Delay circuit employing different threshold FET's | Shigeru Kikuda, Michihiro Yamada | 1991-11-05 |
| 5061030 | Optical integrated modulator | Hideto Iwaoka | 1991-10-29 |
| 4994689 | Semiconductor integrated circuit device | Shigeru Kikuda | 1991-02-19 |
| 4984054 | Electric fuse for a redundancy circuit | Michihiro Yamada, Tadato Yamagata, Shigeru Mori | 1991-01-08 |
| 4974053 | Semiconductor device for multiple packaging configurations | Mitsuya Kinoshita, Tadato Yamagata | 1990-11-27 |
| 4933902 | Method of and apparatus for reducing current of semiconductor memory device | Michihiro Yamada | 1990-06-12 |
| 4931668 | MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform | Shigeru Kikuda, Michihiro Yamada | 1990-06-05 |
| 4920512 | Non-volatile semiconductor memory capable of readily erasing data | — | 1990-04-24 |
| 4914326 | Delay circuit | Shigeru Kikuda, Michihiro Yamada | 1990-04-03 |
| 4904885 | Substrate bias circuit having substrate bias voltage clamp and operating method therefor | Michihiro Yamada, Tadato Yamagata, Shigeru Mori, Tetsuya Aono | 1990-02-27 |
| 4879679 | Dynamic random access memory having storage gate electrode grounding means | Shigeru Kikuda | 1989-11-07 |
| 4870620 | Dynamic random access memory device with internal refresh | Tadato Yamagata, Michihiro Yamada, Shigeru Mori, Tetsuya Aono | 1989-09-26 |
| 4855613 | Wafer scale integration semiconductor device having improved chip power-supply connection arrangement | Michihiro Yamada | 1989-08-08 |
| 4803663 | Semiconductor memory having divided bit lines and individual sense amplifiers | Michihiro Yamada | 1989-02-07 |
| 4792927 | Semiconductor memory device with bit line sense amplifiers | Michihiro Yamada | 1988-12-20 |