Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6430094 | Method for testing a memory device having two or more memory arrays | — | 2002-08-06 |
| 6313658 | Device and method for isolating a short-circuited integrated circuit (IC) from other IC's on a semiconductor wafer | Warren M. Farnworth, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud | 2001-11-06 |
| 6310804 | Device and method for repairing a semiconductor memory | Huy T. Vo | 2001-10-30 |
| 6236614 | Semiconductor memory with local phase generation from global phase signals and local isolation signals | — | 2001-05-22 |
| 6233185 | Wafer level burn-in of memory integrated circuits | Ray Beffa, Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud | 2001-05-15 |
| 6145092 | Apparatus and method implementing repairs on a memory device | Ray Beffa, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud | 2000-11-07 |
| 6134160 | Memory device architecture having global memory array repair capabilities | Kuo-Yuan Hsu | 2000-10-17 |
| 6125067 | Device and method for repairing a semiconductor memory | Huy T. Vo | 2000-09-26 |
| 6104661 | Semiconductor memory with local phase generation from global phase signals and local isolation signals | — | 2000-08-15 |
| 6081467 | Memory device having two or more memory arrays and a testpath operably connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath | — | 2000-06-27 |
| 6079037 | Method and apparatus for detecting intercell defects in a memory device | Ray Beffa | 2000-06-20 |
| 6032264 | Apparatus and method implementing repairs on a memory device | Ray Beffa, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud | 2000-02-29 |
| 6028806 | Semiconductor memory with local phase generation from global phase signals and local isolation signals | — | 2000-02-22 |
| 6005813 | Device and method for repairing a semiconductor memory | Huy T. Vo | 1999-12-21 |
| 5999033 | Low-to-high voltage CMOS driver circuit for driving capacitive loads | Brent Keeth | 1999-12-07 |
| 5930184 | Memory device having two or more memory arrays and a testpath connected to one of the memory arrays and not operably connected to another memory array, and a method of operating the testpath | — | 1999-07-27 |
| 5910921 | Self-test of a memory device | Ray Beffa, Eugene H. Cloud, Warren M. Farnworth, Leland R. Nevill | 1999-06-08 |
| 5898629 | System for stressing a memory integrated circuit die | Ray Beffa, Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud | 1999-04-27 |
| 5883538 | Low-to-high voltage CMOS driver circuit for driving capacitive loads | Brent Keeth | 1999-03-16 |
| 5852581 | Method of stress testing memory integrated circuits | Ray Beffa, Leland R. Nevill, Warren M. Farnworth, Eugene H. Cloud | 1998-12-22 |
| 5787311 | Integrated circuit multiport memory having serial access bit mask register and method for writing in the multiport memory | — | 1998-07-28 |
| 5670905 | Low-to-high voltage CMOS driver circuit for driving capacitive loads | Brent Keeth | 1997-09-23 |
| 5555429 | Multiport RAM based multiprocessor | Ward Parkinson, Mirmajid Seyyedy | 1996-09-10 |
| 5488583 | Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits | Adrian E. Ong, Paul S. Zagar | 1996-01-30 |
| 5475631 | Multiport RAM based multiprocessor | Ward Parkinson, Mirmajid Seyyedy | 1995-12-12 |