Issued Patents All Time
Showing 26–50 of 185 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11200937 | Reprogrammable non-volatile ferroelectric latch for use with a memory controller | Christopher John Kawamura, Charles L. Ingalls | 2021-12-14 |
| 11145358 | Offsetting capacitance of a digit line coupled to storage memory cells coupled to a sense amplifier using offset memory cells | — | 2021-10-12 |
| 11127450 | Pre-writing memory cells of an array | Christopher John Kawamura | 2021-09-21 |
| 11107515 | Ferroelectric memory cells | Christopher John Kawamura | 2021-08-31 |
| 11094697 | Vertical two-transistor single capacitor memory cells and memory arrays | Gloria Yang, Suraj Mathew, Raghunath Singanamalla, Vinay Nair, Michael A. Shore +3 more | 2021-08-17 |
| 11069385 | Integrated assemblies comprising folded-digit-line-configurations | Jiyun Li | 2021-07-20 |
| 11062753 | Array data bit inversion | Charles L. Ingalls | 2021-07-13 |
| 11056165 | Cell-specific reference generation and sensing | Christopher John Kawamura | 2021-07-06 |
| 11031400 | Integrated memory comprising secondary access devices between digit lines and primary access devices | Charles L. Ingalls | 2021-06-08 |
| 11023111 | System, apparatus, and related method for generating a geospatial interactive composite web-based image map | Patrick J. Mullarkey | 2021-06-01 |
| 10998031 | Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory | Christopher John Kawamura | 2021-05-04 |
| 10998027 | Memory circuitry | Charles L. Ingalls, Tae H. Kim | 2021-05-04 |
| 10978126 | Ground reference scheme for a memory cell | Daniele Vimercati, Umberto Di Vincenzo, Christopher Johnson Kawamura, Eric Carman | 2021-04-13 |
| 10957681 | Integrated assemblies comprising sense-amplifier-circuitry and wordline-driver-circuitry under memory cells of a memory array | Hiroki Fujisawa, Charles L. Ingalls, Richard J. Hill, Gurtej S. Sandhu | 2021-03-23 |
| 10957382 | Integrated assemblies comprising vertically-stacked memory array decks and folded digit line connections | Charles L. Ingalls | 2021-03-23 |
| 10950286 | Periphery fill and localized capacitance | Christopher John Kawamura | 2021-03-16 |
| 10943642 | Integrated memory assemblies comprising multiple memory array decks | Charles L. Ingalls | 2021-03-09 |
| 10943624 | Countering digit line coupling in memory arrays | — | 2021-03-09 |
| 10930653 | Apparatuses comprising memory cells, and apparatuses comprising memory arrays | Michael A. Shore, Charles L. Ingalls, Steve V. Cole | 2021-02-23 |
| 10916548 | Memory arrays with vertical access transistors | Charles L. Ingalls | 2021-02-09 |
| 10916295 | Memory arrays with vertical thin film transistors coupled between digit lines | Charles L. Ingalls | 2021-02-09 |
| 10896717 | Pseudo-non-volatile memory cells | Christopher John Kawamura | 2021-01-19 |
| 10885964 | Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory | Christopher John Kawamura | 2021-01-05 |
| 10872650 | Ferroelectric memory cells | Christopher John Kawamura | 2020-12-22 |
| 10867675 | Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells | Michael A. Shore | 2020-12-15 |