Issued Patents All Time
Showing 251–275 of 306 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7271413 | Semiconductor constructions | Randal W. Chance, Gordon A. Haller, Steven D. Cummings | 2007-09-18 |
| 7271086 | Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces | Troy Gugel, John Lee, Fred Fishburn | 2007-09-18 |
| 7244659 | Integrated circuits and methods of forming a field effect transistor | Gordon A. Haller | 2007-07-17 |
| 7242057 | Vertical transistor structures having vertical-surrounding-gates with self-aligned features | Grant S. Huglin | 2007-07-10 |
| 7241655 | Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array | Robert Burke, Anand Srinivasan | 2007-07-10 |
| 7214613 | Cross diffusion barrier layer in polysilicon | Chih-Chen Cho, Robert Burke, Anuradha Iyengar, Eugene Gifford | 2007-05-08 |
| 7211479 | Silicon rich barrier layers for integrated circuit devices | Chris Braun, Farrell M. Good | 2007-05-01 |
| 7170174 | Contact structure and contact liner process | Grant S. Huglin, Robert Burke | 2007-01-30 |
| 7166896 | Cross diffusion barrier layer in polysilicon | Chih-Chen Cho, Robert Burke, Anuradha Iyengar, Eugene Gifford | 2007-01-23 |
| 7160801 | Integrated circuit using a dual poly process | Martin C. Roberts | 2007-01-09 |
| 7122425 | Methods of forming semiconductor constructions | Randal W. Chance, Gordon A. Haller, Steven D. Cummings | 2006-10-17 |
| 7118950 | Method of forming a field effect transistor | Michael P. Violette, Robert Burke | 2006-10-10 |
| 7091654 | Field emission tips, arrays, and devices | Guy T. Blalock, Zhaohui Huang | 2006-08-15 |
| 7071049 | Silicon rich barrier layers for integrated circuit devices | Chris Braun, Farrell M. Good | 2006-07-04 |
| 7071043 | Methods of forming a field effect transistor having source/drain material over insulative material | Michael P. Violette, Robert Burke | 2006-07-04 |
| 6936507 | Method of forming field effect transistors | Michael P. Violette, Robert Burke | 2005-08-30 |
| 6903425 | Silicon rich barrier layers for integrated circuit devices | Chris Braun, Farrell M. Good | 2005-06-07 |
| 6893949 | Semiconductor devices having contact plugs and local interconnects and methods for making the same | Daniel M. Smith, Jason Taylor | 2005-05-17 |
| 6858934 | Semiconductor device structures including metal silicide interconnect structures that extend at least partially over transistor gate structures and methods for making the same | Michael P. Violette | 2005-02-22 |
| 6815825 | Semiconductor devices having gradual slope contacts | — | 2004-11-09 |
| 6759324 | Method of forming a low resistance contact to underlying aluminum interconnect by depositing titanium in a via opening and reacting the titanium with the aluminum | Howard E. Rhodes | 2004-07-06 |
| 6740573 | Method for forming an integrated circuit interconnect using a dual poly process | Martin C. Roberts | 2004-05-25 |
| 6727150 | Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers | — | 2004-04-27 |
| 6713312 | Field emission tips and methods for fabricating the same | Guy T. Blalock, Zhaohui Huang | 2004-03-30 |
| 6703709 | Structures formed using silicide cap as an etch stop in multilayer metal processes | — | 2004-03-09 |