Issued Patents All Time
Showing 276–300 of 306 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6700205 | Semiconductor devices having contact plugs and local interconnects | Daniel M. Smith, Jason Taylor | 2004-03-02 |
| 6693025 | Local interconnect structures for integrated circuits and methods for making the same | Michael P. Violette | 2004-02-17 |
| 6636415 | Capacitor constructions, methods of forming bitlines, and methods of forming capacitor and bitline structures | Raj Narasimhan | 2003-10-21 |
| 6599799 | Double sided container capacitor for DRAM cell array and method of forming same | Robert Burke | 2003-07-29 |
| 6596632 | Method for forming an integrated circuit interconnect using a dual poly process | Martin C. Roberts | 2003-07-22 |
| 6507064 | Double sided container capacitor for DRAM cell array and method of forming same | Robert Burke | 2003-01-14 |
| 6479377 | Method for making semiconductor devices having contact plugs and local interconnects | Daniel M. Smith, Jason Taylor | 2002-11-12 |
| 6437369 | Method of forming dynamic random access memory circuitry and dynamic random access memory | — | 2002-08-20 |
| 6433994 | Capacitor constructions | Raj Narasimhan | 2002-08-13 |
| 6429124 | Local interconnect structures for integrated circuits and methods for making the same | Michael P. Violette | 2002-08-06 |
| 6387717 | Field emission tips and methods for fabricating the same | Guy T. Blalock, Zhaohui Huang | 2002-05-14 |
| 6376380 | Method of forming memory circuitry and method of forming memory circuitry comprising a buried bit line array of memory cells | Raj Narasimhan | 2002-04-23 |
| 6372637 | Method for making semiconductor devices having gradual slope contacts | — | 2002-04-16 |
| 6352916 | Method of forming plugs in multi-level interconnect structures by partially removing conductive material from a trench | Rajendra Narasimhan | 2002-03-05 |
| 6335237 | Methods of forming capacitor and bitline structures | Raj Narasimhan | 2002-01-01 |
| 6274486 | Metal contact and process | Howard E. Rhodes | 2001-08-14 |
| 6268292 | Methods for use in formation of titanium nitride interconnects | Michael P. Violette, Daniel M. Smith | 2001-07-31 |
| 6225698 | Method for making semiconductor devices having gradual slope contacts | — | 2001-05-01 |
| 6200892 | Method for forming an integrated circuit interconnect using a dual poly process | Martin C. Roberts | 2001-03-13 |
| 6162721 | Semiconductor processing methods | — | 2000-12-19 |
| 6160296 | Titanium nitride interconnects | Michael P. Violette, Daniel M. Smith | 2000-12-12 |
| 6143649 | Method for making semiconductor devices having gradual slope contacts | — | 2000-11-07 |
| 6117793 | Using silicide cap as an etch stop for multilayer metal process and structures so formed | — | 2000-09-12 |
| 5977578 | Method of forming dynamic random access memory circuitry and dynamic random access memory | — | 1999-11-02 |
| 5945350 | Methods for use in formation of titanium nitride interconnects and interconnects formed using same | Michael P. Violette, Daniel M. Smith | 1999-08-31 |