Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6627529 | Capacitance reduction by tunnel formation for use with semiconductor device | — | 2003-09-30 |
| 6563219 | Passivation integrity improvements | James E. Green | 2003-05-13 |
| 6531352 | Methods of forming conductive interconnects | Gurtej S. Sandhu, Trung T. Doan, Howard E. Rhodes, Sujit Sharan, Martin C. Roberts | 2003-03-11 |
| 6525426 | Subresolution features for a semiconductor device | — | 2003-02-25 |
| 6479378 | Process for forming electrical interconnects in integrated circuits | — | 2002-11-12 |
| 6444556 | Chemistry for chemical vapor deposition of titanium containing films | Sujit Sharan, Howard E. Rhodes, Gurtej S. Sandhu | 2002-09-03 |
| 6420257 | Process for forming trenches and contacts during the formation of a semiconductor memory device | — | 2002-07-16 |
| 6388284 | Capacitor structures | Howard E. Rhodes, Lyle Breiner, Trung T. Doan, Gurtej S. Sandhu, Sujit Sharan | 2002-05-14 |
| 6365489 | Creation of subresolution features via flow characteristics | — | 2002-04-02 |
| 6358862 | Passivation integrity improvements | James E. Green | 2002-03-19 |
| 6348411 | Method of making a contact structure | Howard E. Rhodes | 2002-02-19 |
| 6331379 | Photo-lithography process using multiple anti-reflective coatings | Thomas R. Glass, Gurtej S. Sandhu | 2001-12-18 |
| 6303492 | Expanded implantation of contact holes | Howard E. Rhodes, Kirk D. Prall, Kenneth N. Hagen | 2001-10-16 |
| 6291289 | Method of forming DRAM trench capacitor with metal layer over hemispherical grain polysilicon | Howard E. Rhodes, Lyle Breiner, Trung T. Doan, Gurtej S. Sandhu, Sujit Sharan | 2001-09-18 |
| 6165889 | Process for forming trenches and contacts during the formation of a semiconductor memory device | — | 2000-12-26 |
| 6110789 | Contact formation using two anneal steps | Howard E. Rhodes, Kenneth N. Hagen, Zhiqiang Wu | 2000-08-29 |
| 5990021 | Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture | Kirk D. Prall, Howard E. Rhodes, Sujit Sharan, Gurtel Sandhu | 1999-11-23 |
| 5751012 | Polysilicon pillar diode for use in a non-volatile memory cell | Graham R. Wolstenholme | 1998-05-12 |
| 5466639 | Double mask process for forming trenches and contacts during the formation of a semiconductor memory device | — | 1995-11-14 |