Issued Patents All Time
Showing 26–50 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11941300 | Integrated pivot table in a logical-to-physical mapping | Giuseppe D'Eliseo, Stephen Hanna | 2024-03-26 |
| 11934692 | Write booster buffer and hibernate | Deping He | 2024-03-19 |
| 11921627 | Usage level identification for memory device addresses | Roberto Izzi, Giuseppe Cariello | 2024-03-05 |
| 11861370 | Automotive boot optimization by utilizing multiple phases of boot-up procedures | Roberto Izzi, Dionisio Minopoli | 2024-01-02 |
| 11847353 | Suspend operation with data transfer to host system | Jonathan S. Parry, Christian M. Gyllenskog | 2023-12-19 |
| 11847468 | Data defragmentation for a system boot procedure having random indexes indicating a relationship between sequential logical addresses and random logical addresses | Francesco Basso, Roberto Izzi, Francesco Falanga, Nadav Grosz, Massimo Iaculo | 2023-12-19 |
| 11835992 | Hybrid memory system interface | Danilo Caraccio, Marco Dallabora, Daniele Balluchi, Paolo Amato | 2023-12-05 |
| 11829646 | Memory device performance based on storage traffic pattern detection | Nicola Colella, Dionisio Minopoli | 2023-11-28 |
| 11790961 | Memory device access techniques | Giuseppe Cariello | 2023-10-17 |
| 11768629 | Techniques for memory system configuration using queue refill time | Nadav Grosz, Roberto Izzi, Jonathan S. Parry | 2023-09-26 |
| 11755490 | Unmap operation techniques | Giuseppe Cariello, Roberto Izzi, Jonathan S. Parry | 2023-09-12 |
| 11740837 | Storage traffic pattern detection in memory devices | Roberto Izzi, Nicola Colella, Danilo Caraccio, Alessandro Orlando | 2023-08-29 |
| 11727969 | Memory sub-system managing remapping for misaligned memory components | Marco Di Pasqua, Paolo Papa | 2023-08-15 |
| 11704049 | Optimized command sequences | Christian M. Gyllenskog | 2023-07-18 |
| 11663062 | Detecting page fault traffic | Alessandro Orlando, Danilo Caraccio, Roberto Izzi | 2023-05-30 |
| 11520525 | Integrated pivot table in a logical-to-physical mapping having entries and subsets associated via a flag | Giuseppe D'Eliseo, Stephen Hanna | 2022-12-06 |
| 11379153 | Storage traffic pattern detection in memory devices | Roberto Izzi, Nicola Colella, Danilo Caraccio, Alessandro Orlando | 2022-07-05 |
| 11347402 | Performing wear leveling operations in a memory based on block cycles and use of spare blocks | Domenico Monteleone, Giacomo Bernardi, Graziano Mirichigni, Stefano Zanardi, Erminio Di Martino | 2022-05-31 |
| 11340808 | Latency-based storage in a hybrid memory system | Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato +1 more | 2022-05-24 |
| 11327892 | Latency-based storage in a hybrid memory system | Danilo Caraccio, Emanuele Confalonieri, Marco Dallabora, Roberto Izzi, Paolo Amato +1 more | 2022-05-10 |
| 11314456 | Memory device performance based on storage traffic pattern detection | Nicola Colella, Dionisio Minopoli | 2022-04-26 |
| 11249830 | Detecting page fault traffic | Alessandro Orlando, Danilo Caraccio, Roberto Izzi | 2022-02-15 |
| 11222673 | Memory sub-system managing remapping for misaligned memory components | Marco Di Pasqua, Paolo Papa | 2022-01-11 |
| 11151027 | Methods and apparatuses for requesting ready status information from a memory | Graziano Mirichigni, Danilo Caraccio | 2021-10-19 |
| 11023167 | Methods and apparatuses for executing a plurality of queued tasks in a memory | Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Antonino Pollio | 2021-06-01 |