Issued Patents All Time
Showing 151–175 of 522 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7990775 | Methods of operating memory devices including different sets of logical erase blocks | — | 2011-08-02 |
| 7986553 | Programming of a solid state memory utilizing analog communication of bit patterns | — | 2011-07-26 |
| 7961522 | Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells | — | 2011-06-14 |
| 7961518 | Programming rate identification and control in a solid state memory | — | 2011-06-14 |
| 7957196 | Method of programming memory cells of series strings of memory cells | Vishal Sarin, Jung Sheng Hoei | 2011-06-07 |
| 7952924 | NAND memory device and programming methods | Ebrahim Abedifard | 2011-05-31 |
| 7936608 | Memory device operation | — | 2011-05-03 |
| 7936599 | Coarse and fine programming in a solid state memory | Vishal Sarin, Jung Sheng Hoei | 2011-05-03 |
| 7916536 | Programming based on controller performance requirements | Vishal Sarin, Jung Sheng Hoei | 2011-03-29 |
| 7913033 | Non-volatile memory device having assignable network identification | — | 2011-03-22 |
| 7907444 | Memory device reference cell programming method and apparatus | Vishal Sarin | 2011-03-15 |
| 7903463 | Increased NAND flash memory read throughput | Dzung H. Nguyen | 2011-03-08 |
| 7898885 | Analog sensing of memory cells in a solid state memory device | Vishal Sarin, Jung Sheng Hoei | 2011-03-01 |
| 7894271 | Sensing of memory cells in a solid state memory device by fixed discharge of a bit line | — | 2011-02-22 |
| 7876622 | Read method for MLC | — | 2011-01-25 |
| 7872911 | Non-volatile multilevel memory cells with data read of reference cells | Vishal Sarin, Jung Sheng Hoei | 2011-01-18 |
| 7872912 | M+N bit programming and M+L bit read for M bit memory cells | Vishal Sarin, Jung Sheng Hoei | 2011-01-18 |
| 7864589 | Mitigation of runaway programming of a memory device | Vishal Sarin, Jonathan Pabustan | 2011-01-04 |
| 7864587 | Programming a memory device to increase data reliability | — | 2011-01-04 |
| 7843725 | M+L bit read column architecture for M bit memory cells | Vishal Sarin, Jung Sheng Hoei, Jonathan Pabustan | 2010-11-30 |
| 7843726 | Sensing against a reference cell | Vishal Sarin | 2010-11-30 |
| 7844811 | Using chip select to specify boot memory | Cliff Zitlaw, David Eggleston | 2010-11-30 |
| 7830718 | Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device | Vishal Sarin, Jung Sheng Hoei | 2010-11-09 |
| 7826290 | Apparatus and method for increasing data line noise tolerance | Chia-Shing Jason Yu, Jung Sheng Hoei, Vishal Sarin | 2010-11-02 |
| 7817467 | Memory controller self-calibration for removing systemic influence | Vishal Sarin, Jung Sheng Hoei | 2010-10-19 |