Issued Patents All Time
Showing 201–225 of 522 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7633798 | M+N bit programming and M+L bit read for M bit memory cells | Vishal Sarin, Jung Sheng Hoei | 2009-12-15 |
| 7630246 | Programming rate identification and control in a solid state memory | — | 2009-12-08 |
| 7630240 | Read method for MLC | — | 2009-12-08 |
| 7610525 | Defective memory block identification in a memory device | — | 2009-10-27 |
| 7609560 | Sensing of memory cells in a solid state memory device by fixed discharge of a bit line | — | 2009-10-27 |
| 7603534 | Synchronous flash memory with status burst output | — | 2009-10-13 |
| 7586784 | Apparatus and methods for programming multilevel-cell NAND memory devices | — | 2009-09-08 |
| 7573738 | Mode selection in a flash memory device | — | 2009-08-11 |
| 7567461 | Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells | — | 2009-07-28 |
| 7564721 | Method and apparatus for improving storage performance using a background erase | — | 2009-07-21 |
| 7561466 | Non-volatile memory copy back | — | 2009-07-14 |
| 7551481 | User configurable commands for flash memory | — | 2009-06-23 |
| 7551467 | Memory device architectures and operation | — | 2009-06-23 |
| 7535759 | Memory system with user configurable density/performance option | — | 2009-05-19 |
| 7529129 | Single level cell programming in a multiple level cell non-volatile memory device | — | 2009-05-05 |
| 7525842 | Increased NAND flash memory read throughput | Dzung H. Nguyen | 2009-04-28 |
| 7508708 | NAND string with a redundant memory cell | — | 2009-03-24 |
| 7489546 | NAND architecture memory devices and operation | — | 2009-02-10 |
| 7483330 | Power efficient memory and cards | — | 2009-01-27 |
| 7471535 | Programable identification circuitry | — | 2008-12-30 |
| 7466600 | System and method for initiating a bad block disable process in a non-volatile memory | — | 2008-12-16 |
| 7460398 | Programming a memory with varying bits per cell | Vishal Sarin, Jung Sheng Hoei | 2008-12-02 |
| 7461306 | Output data compression scheme using tri-state | — | 2008-12-02 |
| 7457169 | Flash with consistent latency for read operations | — | 2008-11-25 |
| 7450422 | NAND architecture memory devices and operation | — | 2008-11-11 |