Issued Patents All Time
Showing 301–314 of 314 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5192703 | Method of making tungsten contact core stack capacitor | Roger Lee | 1993-03-09 |
| 5177027 | Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path | Tyler Lowrey, Randal W. Chance, D. Mark Durcan, Pierre C. Fazan, Gordon A. Haller | 1993-01-05 |
| 5168073 | Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate | Roger Lee | 1992-12-01 |
| 5150276 | Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings | Larry D. Cromar | 1992-09-22 |
| 5122848 | Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance | Ruojia Lee | 1992-06-16 |
| 5057449 | Process for creating two thicknesses of gate oxide within a dynamic random access memory | Tyler Lowrey, Joseph Karniewicz | 1991-10-15 |
| 5037773 | Stacked capacitor doping technique making use of rugged polysilicon | Ruojia Lee | 1991-08-06 |
| 5030585 | Split-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formation | Joseph Karniewicz | 1991-07-09 |
| 5026657 | Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions | Ruojia Lee, Tyler Lowrey, Joseph Karniewicz, Pierre C. Fazan | 1991-06-25 |
| 5023190 | CMOS processes | Ruojia Lee | 1991-06-11 |
| 5013680 | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography | Tyler Lowrey, Randal W. Chance, D. Mark Durcan, Ruojia Lee, Charles H. Dennison +3 more | 1991-05-07 |
| 5005072 | Stacked cell design for 16-megabit DRAM array having a pair of interconnected poly layers which enfold a single field plate layer and connect to the cell's storage node junction | — | 1991-04-02 |
| 4965221 | Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions | Charles H. Dennison | 1990-10-23 |
| 4864464 | Low-profile, folded-plate dram-cell capacitor fabricated with two mask steps | — | 1989-09-05 |