Issued Patents All Time
Showing 76–100 of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10818666 | Gate noble metal nanoparticles | Kamal M. Karda, Haitao Liu | 2020-10-27 |
| 10672785 | Integrated structures of vertically-stacked memory cells | Meng-Wei Kuo, John D. Hopkins | 2020-06-02 |
| 10600807 | Integrated structures and methods of forming vertically-stacked memory cells | Jie Sun | 2020-03-24 |
| 10553703 | Array of elevationally-extending transistors and a method used in forming an array of elevationally-extending transistors | Diem Thy N. Tran | 2020-02-04 |
| 10529776 | Cell pillar structures and integrated flows | Krishna K. Parat | 2020-01-07 |
| 10515972 | Memory cell pillar including source junction plug | Krishna K. Parat, Luan C. Tran, Meng-Wei Kuo, Yushi Hu | 2019-12-24 |
| 10411017 | Multi-component conductive structures for semiconductor devices | Eric Blomiley | 2019-09-10 |
| 10388668 | Integrated structures and methods of forming vertically-stacked memory cells | Jie Sun | 2019-08-20 |
| 10381363 | Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells including metal | Akira Goda, Durai Vishak Nirmal Ramaswamy | 2019-08-13 |
| 10355008 | Floating gate memory cells in vertical memory | Charles H. Dennison, Akira Goda, John D. Hopkins, Krishna K. Parat | 2019-07-16 |
| 10319724 | Memory cells and memory arrays | Suraj Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed +1 more | 2019-06-11 |
| 10217799 | Cell pillar structures and integrated flows | Krishna K. Parat | 2019-02-26 |
| 10170639 | 3D memory | John D. Hopkins, Darwin Franseda Fan, James C. Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti | 2019-01-01 |
| 10170491 | Memory including blocking dielectric in etch stop tier | John D. Hopkins, Srikant Jayanti | 2019-01-01 |
| 10157926 | Memory cells and memory arrays | Gloria Yang, Suraj Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner +3 more | 2018-12-18 |
| 10153298 | Integrated structures and methods of forming vertically-stacked memory cells | Jie Sun | 2018-12-11 |
| 10141322 | Metal floating gate composite 3D NAND memory devices and associated methods | Nirmal Ramaswamy | 2018-11-27 |
| 10103160 | Semiconductor structures including dielectric materials having differing removal rates | Srikant Jayanti, Pavan Kumar Reddy Aella | 2018-10-16 |
| 10090317 | Methods and apparatuses having memory cells including a monolithic semiconductor channel | Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John D. Hopkins +3 more | 2018-10-02 |
| 10079235 | Memory cells and memory arrays | Suraj Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair +2 more | 2018-09-18 |
| 10056386 | Memory cells and memory arrays | Suraj Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed +1 more | 2018-08-21 |
| 10002767 | Aluminum oxide landing layer for conductive channels for a three dimensional circuit device | Hongbin Zhu, Gordon A. Haller | 2018-06-19 |
| 9991273 | Floating gate memory cells in vertical memory | Charles H. Dennison, Akira Goda, John D. Hopkins, Krishna K. Parat | 2018-06-05 |
| 9899413 | Integrated structures and methods of forming vertically-stacked memory cells | Jie Sun | 2018-02-20 |
| 9793282 | Floating gate memory cells in vertical memory | Charles H. Dennison, Akira Goda, John D. Hopkins, Krishna K. Parat | 2017-10-17 |