Issued Patents All Time
Showing 101–125 of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9780102 | Memory cell pillar including source junction plug | Krishna K. Parat, Luan C. Tran, Meng-Wei Kuo, Yushi Hu | 2017-10-03 |
| 9773841 | Cell pillar structures and integrated flows | Krishna K. Parat | 2017-09-26 |
| 9722074 | Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling | Randy J. Koval | 2017-08-01 |
| 9634025 | Integrated structures and methods of forming vertically-stacked memory cells | Jie Sun | 2017-04-25 |
| 9595531 | Aluminum oxide landing layer for conductive channels for a three dimensional circuit device | Hongbin Zhu, Gordon A. Haller | 2017-03-14 |
| 9559109 | Memory including blocking dielectric in etch stop tier | John D. Hopkins, Srikant Jayanti | 2017-01-31 |
| 9478643 | Memory structure with self-aligned floating and control gates and associated methods | John D. Hopkins | 2016-10-25 |
| 9455261 | Integrated structures | Jie Sun | 2016-09-27 |
| 9431410 | Methods and apparatuses having memory cells including a monolithic semiconductor channel | Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John D. Hopkins +3 more | 2016-08-30 |
| 9412821 | Stacked thin channels for boost and leakage improvement | Jie Sun, Benben Li, Srikant Jayanti, Han Zhao, Guangyu Huang +1 more | 2016-08-09 |
| 9384995 | Tungsten salicide gate source for vertical NAND string to control on current and cell pillar fabrication | Krishna K. Parat | 2016-07-05 |
| 9305938 | Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells | Aaron R. Wilson | 2016-04-05 |
| 9276011 | Cell pillar structures and integrated flows | Krishna K. Parat | 2016-03-01 |
| 9275909 | Methods of fabricating semiconductor structures | Srikant Jayanti, Pavan Kumar Reddy Aella | 2016-03-01 |
| 9230986 | 3D memory | John D. Hopkins, Darwin Franseda Fan, James C. Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti | 2016-01-05 |
| 9209199 | Stacked thin channels for boost and leakage improvement | Jie Sun, Benben Li, Srikant Jayanti, Han Zhao, Guangyu Huang +1 more | 2015-12-08 |
| 9190490 | Local buried channel dielectric for vertical NAND performance enhancement and vertical scaling | Randy J. Koval | 2015-11-17 |
| 9184175 | Floating gate memory cells in vertical memory | Charles H. Dennison, Akira Goda, John D. Hopkins, Krishna K. Parat | 2015-11-10 |
| 9136278 | Methods of forming vertically-stacked memory cells | Aaron R. Wilson | 2015-09-15 |
| 9064970 | Memory including blocking dielectric in etch stop tier | John D. Hopkins, Srikant Jayanti | 2015-06-23 |
| 9041090 | Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells including metal | Akira Goda, Durai Vishak Nirmal Ramaswamy | 2015-05-26 |
| 8980752 | Method of forming a plurality of spaced features | Farrell M. Good, Baosuo Zhou, Xiaolong Fang | 2015-03-17 |
| 8969948 | Tungsten salicide gate source for vertical NAND string to control on current and cell pillar fabrication | Krishna K. Parat | 2015-03-03 |
| 8946076 | Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells | Aaron R. Wilson | 2015-02-03 |
| 8946807 | 3D memory | John D. Hopkins, Darwin Franseda Fan, James C. Brighten, Aurelio Giancarlo Mauri, Srikant Jayanti | 2015-02-03 |