Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Eric T. Stubbs — 43 Patents

Micron: 43 patents #441 of 6,374Top 7%
Boise, ID: #254 of 3,546 inventorsTop 8%
Idaho: #340 of 8,810 inventorsTop 4%
Overall (All Time): #69,380 of 4,157,543Top 2%
43 Patents All Time
Eric T. Stubbs has been granted 43 US patents while listed as an inventor at Micron. The first was granted in 1998 and the most recent in July 2008. Eric T. Stubbs ranks #69,380 of 4,157,543 US inventors in our database (top 1.7%). Patent records list Eric T. Stubbs in Boise, ID, US.

Patents per Year

Patents granted per year, 1998 to 2008Bar chart with a peak of 7 patents in 2002.peak 71998: 2 patents19981999: 4 patents2000: 4 patents20002001: 6 patents2002: 7 patents20022003: 7 patents2004: 3 patents20042005: 6 patents2006: 2 patents20062007: 1 patents2008: 1 patents2008

Issued Patents All Time

Showing 1–25 of 43 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7400544 Actively driven VREF for input buffer noise immunity James E. Miller 2008-07-15 $1,858,000
7274605 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM 2007-09-25 $1,063,000
7152143 Integrated semiconductor memory chip with presence detect data capability Gordon D. Roberts 2006-12-19 $2,309,000
7116589 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM 2006-10-03 $1,273,000
6959062 Variable delay line 2005-10-25 $2,371,000
6947341 Integrated semiconductor memory chip with presence detect data capability Gordon D. Roberts 2005-09-20 $1,200,000
6898144 Actively driven VREF for input buffer noise immunity James E. Miller 2005-05-24 $1,184,000
6882587 Method of preparing to test a capacitor Kurt D. Beigel, Manny K. F. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer +1 more 2005-04-19 $902,000
6862224 System and method for operating a memory array 2005-03-01 $1,260,000
6838712 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM 2005-01-04 $1,193,000
6791381 Method and apparatus for reducing the lock time of a DLL James E. Miller 2004-09-14 $1,322,000
6778452 Circuit and method for voltage regulation in a semiconductor device Kurt D. Beigel, Douglas J. Cutter, Manny K. F. Ma, Gordon D. Roberts, James E. Miller +2 more 2004-08-17 $1,525,000
6727739 Compensation for a delay locked loop Christopher K. Morzano 2004-04-27 $2,268,000
6667911 High speed memory architecture 2003-12-23 $5,142,000
6636093 Compensation for a delay locked loop Christopher K. Morzano 2003-10-21 $3,052,000
6625692 Integrated semiconductor memory chip with presence detect data capability Gordon D. Roberts 2003-09-23 $3,145,000
6600687 Method of compensating for a defect within a semiconductor device Kurt D. Beigel, Manny K. F. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer +1 more 2003-07-29 $3,127,000
6597619 Actively driven VREF for input buffer noise immunity James E. Miller 2003-07-22 $3,963,000
6581174 On-chip testing circuit and method for integrated circuits 2003-06-17 $4,055,000
6570258 Method for reducing capacitive coupling between conductive lines Kin F. Ma 2003-05-27 $3,176,000
6469944 Method of compensating for a defect within a semiconductor device Kurt D. Beigel, Manny K. F. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer +1 more 2002-10-22 $4,725,000
6452846 Driver circuit for a voltage-pulling device Kurt D. Beigel, Douglas J. Cutter, Manny K. F. Ma, Gordon D. Roberts, James E. Miller +2 more 2002-09-17 $3,284,000
6445629 Method of stressing a memory device Kurt D. Beigel, Douglas J. Cutter, Manny K. F. Ma, Gordon D. Roberts, James E. Miller +2 more 2002-09-03 $3,391,000
6418071 Method of testing a memory cell Kurt D. Beigel, Manny K. F. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer +1 more 2002-07-09 $4,358,000
6388480 Method and apparatus for reducing the lock time of DLL James E. Miller 2002-05-14 $7,837,000