Issued Patents All Time
Showing 101–125 of 295 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6552401 | Use of gate electrode workfunction to improve DRAM refresh | — | 2003-04-22 |
| RE38049 | Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing | Michael A. Walker | 2003-03-25 |
| 6537891 | Silicon on insulator DRAM process utilizing both fully and partially depleted devices | John K. Zahurak | 2003-03-25 |
| 6534781 | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact | — | 2003-03-18 |
| 6524907 | Method of reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Jeffrey W. Honeycutt | 2003-02-25 |
| 6511867 | Utilizing atomic layer deposition for programmable device | Tyler Lowrey | 2003-01-28 |
| 6501114 | Structures comprising transistor gates | Chih-Chen Cho, Richard H. Lane | 2002-12-31 |
| 6498375 | Integrated circuitry | — | 2002-12-24 |
| 6495885 | Graded LDD implant process for sub-half-micron MOS devices | Aftab Ahmad | 2002-12-17 |
| 6482707 | Method of improving static refresh | Mark Fischer, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh | 2002-11-19 |
| 6479332 | Methods of forming integrated circuitry | Monte Manning | 2002-11-12 |
| 6476490 | Contact openings, electrical connections and interconnections for integrated circuitry | — | 2002-11-05 |
| 6468859 | Method of reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Jeffrey W. Honeycutt | 2002-10-22 |
| 6468883 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections | — | 2002-10-22 |
| 6465331 | DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines | Brent Keeth | 2002-10-15 |
| RE37865 | Semiconductor electrical interconnection methods | — | 2002-10-01 |
| 6448141 | Graded LDD implant process for sub-half-micron MOS devices | Aftab Ahmad | 2002-09-10 |
| 6444520 | Method of forming dual conductive plugs | Raymond A. Turi | 2002-09-03 |
| 6445636 | Method and system for hiding refreshes in a dynamic random access memory | Brent Keeth, Brian M. Shirley, Kevin J. Ryan | 2002-09-03 |
| 6440850 | Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same | Kunal R. Parekh, Mark Fischer | 2002-08-27 |
| 6438016 | Semiconductor memory having dual port cell supporting hidden refresh | Brent Keeth | 2002-08-20 |
| 6429069 | SOI DRAM with buried capacitor under the digit lines utilizing a self aligning penetrating storage node contact formation | John K. Zahurak | 2002-08-06 |
| 6420250 | Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates | Chih-Chen Cho, Richard H. Lane | 2002-07-16 |
| 6414392 | Integrated circuit contact | Trung T. Doan | 2002-07-02 |
| 6410951 | Structure for improving static refresh | Mark Fischer, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh | 2002-06-25 |