Issued Patents All Time
Showing 51–75 of 295 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE39665 | Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing | Michael A. Walker | 2007-05-29 |
| 7217945 | Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby | Chien Chiang | 2007-05-15 |
| 7196351 | Forming phase change memories | Chien-Chih Chiang, Tyler Lowrey | 2007-03-27 |
| 7155561 | Method and system for using dynamic random access memory as cache memory | Brent Keeth, Brian M. Shirley | 2006-12-26 |
| 7119397 | Double blanket ion implant method and structure | Mark Fischer, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh | 2006-10-10 |
| 7105408 | Phase change memory with a select device having a breakdown layer | — | 2006-09-12 |
| 7064036 | Dual-gate transistor device and method of forming a dual-gate transistor device | John K. Zahurak, Brent Keeth | 2006-06-20 |
| 7005666 | Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby | — | 2006-02-28 |
| 6990017 | Accessing phase change memories | Ward Parkinson, Stephen J. Hudgens | 2006-01-24 |
| 6969633 | Lower electrode isolation in a double-wide trench and method of making same | — | 2005-11-29 |
| 6967146 | Isolation region forming methods | David Dickerson, Richard H. Lane, Kunal R. Parekh, Mark Fischer, John K. Zahurak | 2005-11-22 |
| 6948027 | Method and system for using dynamic random access memory as cache memory | Brent Keeth, Brian M. Shirley, Kevin J. Ryan | 2005-09-20 |
| 6939799 | Method of forming a field effect transistor and methods of forming integrated circuitry | — | 2005-09-06 |
| 6924190 | Use of gate electrode workfunction to improve DRAM refresh | — | 2005-08-02 |
| 6919578 | Utilizing atomic layer deposition for programmable device | Tyler Lowrey | 2005-07-19 |
| 6897542 | Semiconductor assemblies | — | 2005-05-24 |
| 6894332 | Apparatus for reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Jeffrey W. Honeycutt | 2005-05-17 |
| 6882017 | Field effect transistors and integrated circuitry | — | 2005-04-19 |
| 6869883 | Forming phase change memories | Chien-Chih Chiang, Tyler Lowrey | 2005-03-22 |
| 6862654 | Method and system for using dynamic random access memory as cache memory | Brent Keeth, Brian M. Shirley, Kevin J. Ryan | 2005-03-01 |
| 6858507 | Graded LDD implant process for sub-half-micron MOS devices | Aftab Ahmad | 2005-02-22 |
| 6855628 | Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry | — | 2005-02-15 |
| 6833291 | Semiconductor processing methods | — | 2004-12-21 |
| 6818496 | Silicon on insulator DRAM process utilizing both fully and partially depleted devices | John K. Zahurak | 2004-11-16 |
| 6808982 | Method of reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Jeffrey W. Honeycutt | 2004-10-26 |