Issued Patents All Time
Showing 301–325 of 354 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7247932 | Chip package with capacitor | Bryan Peng | 2007-07-24 |
| 7242099 | Chip package with multiple chips connected by bumps | Shih-Hsiung Lin | 2007-07-10 |
| 7230340 | Post passivation interconnection schemes on top of the IC chips | — | 2007-06-12 |
| 7205646 | Electronic device and chip package | Bryan Peng | 2007-04-17 |
| 7045901 | Chip-on-chip connection with second chip located in rectangular open window hole in printed circuit board | Bryan Peng | 2006-05-16 |
| 6965165 | Top layers of metal for high performance IC's | — | 2005-11-15 |
| 6939747 | Multiple selectable function integrated circuit module | — | 2005-09-06 |
| 6936531 | Process of fabricating a chip structure | Jin-Yuan Lee, Ching-Cheng Huang | 2005-08-30 |
| 6897507 | Capacitor for high performance system-on-chip using post passivation device | — | 2005-05-24 |
| 6869870 | High performance system-on-chip discrete components using post passivation process | — | 2005-03-22 |
| 6818545 | Low fabrication cost, fine pitch and high reliability solder bump | Jin-Yuan Lee, Ching-Cheng Huang | 2004-11-16 |
| 6815324 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei | 2004-11-09 |
| 6800941 | Integrated chip package structure using ceramic substrate and method of manufacturing the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-10-05 |
| 6798073 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-09-28 |
| 6791192 | Multiple chips bonded to packaging structure with low noise and multiple selectable functions | Bryan Peng | 2004-09-14 |
| 6768208 | Multiple chips bonded to packaging structure with low noise and multiple selectable functions | Bryan Peng | 2004-07-27 |
| 6762115 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-07-13 |
| 6759275 | Method for making high-performance RF integrated circuits | Jin-Yuan Lee | 2004-07-06 |
| 6756295 | Chip structure and process for forming the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-06-29 |
| 6746898 | Integrated chip package structure using silicon substrate and method of manufacturing the same | Jin-Yuan Lee, Ching-Cheng Huang | 2004-06-08 |
| 6734563 | Post passivation interconnection schemes on top of the IC chips | Jin-Yuan Lee | 2004-05-11 |
| 6700162 | Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip | Jin-Yuan Lee, Ching-Cheng Huang | 2004-03-02 |
| 6673698 | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers | Jin-Yuan Lee, Ching-Cheng Huang | 2004-01-06 |
| 6657310 | Top layers of metal for high performance IC's | — | 2003-12-02 |
| 6649509 | Post passivation metal scheme for high-performance integrated circuit devices | Ming-Ta Lei, Jin-Yuan Lee, Ching-Cheng Huang | 2003-11-18 |