Issued Patents All Time
Showing 1–25 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7605414 | MOS transistors having low-resistance salicide gates and a self-aligned contact between them | — | 2009-10-20 |
| 7541271 | MOS transistors having low-resistance salicide gates and a self-aligned contact between them and method of manufacture | — | 2009-06-02 |
| 7361604 | Method for reducing dimensions between patterns on a hardmask | Shin-Yi Tsai, Ming-Chung Liang | 2008-04-22 |
| 7303995 | Method for reducing dimensions between patterns on a photoresist | Shin-Yi Tsai, Ming-Chung Liang | 2007-12-04 |
| 7105099 | Method of reducing pattern pitch in integrated circuits | Ming-Chung Liang, An-Chi Wei, Shin-Yi Tsai, Kuo-Liang Wei | 2006-09-12 |
| 7033948 | Method for reducing dimensions between patterns on a photoresist | Shin-Yi Tsai, Ming-Chung Liang | 2006-04-25 |
| 6998316 | Method for fabricating read only memory including a first and second exposures to a photoresist layer | Tahorng Yang, Cheng-Chen Calvin Hsueh, Ching-Yu Chang | 2006-02-14 |
| 6955961 | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution | — | 2005-10-18 |
| 6946400 | Patterning method for fabricating integrated circuit | — | 2005-09-20 |
| 6887627 | Method of fabricating phase shift mask | Chi-Yuan Hung, Ching-Yu Chang, I-Pien Wu | 2005-05-03 |
| 6867116 | Fabrication method of sub-resolution pitch for integrated circuits | — | 2005-03-15 |
| 6812131 | Use of sacrificial inorganic dielectrics for dual damascene processes utilizing organic intermetal dielectrics | Joseph Kennedy, Anna George | 2004-11-02 |
| 6809018 | Dual salicides for integrated circuits | — | 2004-10-26 |
| 6790743 | [Method to relax alignment accuracy requirement in fabrication for integrated circuit] | — | 2004-09-14 |
| 6774051 | Method for reducing pitch | Chia-Chi Chung, Ming-Chung Liang, Jerry Lai | 2004-08-10 |
| 6770975 | Integrated circuits with multiple low dielectric-constant inter-metal dielectrics | Shi-Qing Wang, James Hao-An Chen Lin | 2004-08-03 |
| 6750150 | Method for reducing dimensions between patterns on a photoresist | Shin-Yi Tsai, Ming-Chung Liang | 2004-06-15 |
| 6734064 | Method for fabricating read only memory including forming masking layers with openings and pre-coding the cell and peripheral regions | Tahorng Yang, Cheng-Chen Calvin Hsueh, Ching-Yu Chang | 2004-05-11 |
| 6713354 | Coding method for mask ROM | — | 2004-03-30 |
| 6709923 | Method for manufacturing an array structure in integrated circuits | — | 2004-03-23 |
| 6642139 | Method for forming interconnection structure in an integration circuit | — | 2003-11-04 |
| 6559045 | Fabrication of integrated circuits with borderless vias | — | 2003-05-06 |
| 6504247 | Integrated having a self-aligned Cu diffusion barrier | — | 2003-01-07 |
| 6498399 | Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits | James Hao-An Chen Lin | 2002-12-24 |
| 6472124 | Self-aligned metal-insulator-metal capacitor for integrated circuits | — | 2002-10-29 |