Issued Patents All Time
Showing 126–150 of 250 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8935594 | Structure of ECC spare bits in 3D memory | Shih-Hung Chen, I-Jen Huang | 2015-01-13 |
| 8922020 | Integrated circuit pattern and method | Shih-Hung Chen | 2014-12-30 |
| 8890233 | 3D memory array with improved SSL and BL contact layout | Chun-Hsiung Hung, Shin-Jang Shen | 2014-11-18 |
| 8889509 | Charge trapping devices with field distribution layer over tunneling barrier | — | 2014-11-18 |
| 8860124 | Depletion-mode charge-trapping flash device | Yi-Hsuan Hsiao | 2014-10-14 |
| 8861273 | Bandgap engineered charge trapping memory in two-transistor nor architecture | — | 2014-10-14 |
| 8853818 | 3D NAND flash memory | — | 2014-10-07 |
| 8846549 | Method of forming bottom oxide for nitride flash memory | Yen-Hao Shih, Erh-Kun Lai, Kuang Yeu Hsieh | 2014-09-30 |
| 8829646 | Integrated circuit 3D memory array and manufacturing method | Hsiang-Lan Lung | 2014-09-09 |
| 8824212 | Thermally assisted flash memory with segmented word lines | — | 2014-09-02 |
| 8811077 | Memory architecture of 3D array with improved uniformity of bit line capacitances | Chun-Hsiung Hung, Shih-Hung Chen | 2014-08-19 |
| 8780602 | Integrated circuit self aligned 3D memory array and manufacturing method | — | 2014-07-15 |
| 8772858 | Vertical channel memory and manufacturing method thereof and operating method using the same | Tzu-Hsuan Hsu | 2014-07-08 |
| 8760928 | NAND flash biasing operation | Ti Wen Chen, Shuo-Nan Hung, Shih-Lin HUANG, Chih-Chang Hsieh, Kuo-Pin Chang | 2014-06-24 |
| 8759899 | Integration of 3D stacked IC device with peripheral circuits | Yi-Hsuan Hsiao, Shih-Hung Chen, Yen-Hao Shih | 2014-06-24 |
| 8724393 | Thermally assisted flash memory with diode strapping | Chun-Hsiung Hung | 2014-05-13 |
| 8705278 | One-transistor cell semiconductor on insulator random access memory | — | 2014-04-22 |
| 8704205 | Semiconductor structure with improved capacitance of bit line | Shih-Hung Chen, Kuang Yeu Hsieh, Erh-Kun Lai, Yen-Hao Shih | 2014-04-22 |
| 8675381 | Transistor having an adjustable gate resistance and semiconductor device comprising the same | Kuo-Pin Chang | 2014-03-18 |
| 8659944 | Memory architecture of 3D array with diode in memory string | Chun-Hsiung Hung, Shin-Jang Shen | 2014-02-25 |
| 8643078 | Semiconductor structure and manufacturing method of the same | Shih-Hung Chen, Kuang Yeu Hsieh | 2014-02-04 |
| 8644077 | Memory device, manufacturing method and operating method of the same | Shih-Hung Chen | 2014-02-04 |
| 8630114 | Memory architecture of 3D NOR array | — | 2014-01-14 |
| 8609554 | Semiconductor structure and method for manufacturing the same | Yi-Hsuan Hsiao | 2013-12-17 |
| 8598032 | Reduced number of masks for IC device with stacked contact levels | Shih-Hung Chen | 2013-12-03 |