Issued Patents All Time
Showing 151–175 of 250 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8574992 | Contact architecture for 3D memory array | Shih-Hung Chen, Yen-Hao Shih | 2013-11-05 |
| 8547741 | Nonvolatile stacked NAND memory | Yi-Hsuan Hsiao | 2013-10-01 |
| 8503213 | Memory architecture of 3D array with alternating memory string orientation and string select structures | Shih-Hung Chen | 2013-08-06 |
| 8501574 | Resistive memory device and manufacturing method thereof and operating method thereof | Kuo-Pin Chang, Cheng-Hung Tsai | 2013-08-06 |
| 8488387 | Thermally assisted dielectric charge trapping flash | Chih-Ping Chen, Chih-Chang Hsieh, Yi-Hsuan Hsiao | 2013-07-16 |
| 8486791 | Mufti-layer single crystal 3D stackable memory | — | 2013-07-16 |
| 8481388 | Non-volatile memory device having a nitride-oxide dielectric layer | Chao-I Wu, Tzu-Hsuan Hsu, Erh-Kun Lai | 2013-07-09 |
| 8482052 | Silicon on insulator and thin film transistor bandgap engineered split gate memory | Erh-Kun Lai | 2013-07-09 |
| 8467219 | Integrated circuit self aligned 3D memory array and manufacturing method | — | 2013-06-18 |
| 8437192 | 3D two bit-per-cell NAND flash memory | Hsiang-Lan Lung, Yen-Hao Shih, Erh-Kun Lai, Ming-Hsiu Lee, Tien-Yen Wang | 2013-05-07 |
| 8432719 | Three-dimensional stacked and-type flash memory structure and methods of manufacturing and operating the same hydride | — | 2013-04-30 |
| 8426294 | 3D memory array arranged for FN tunneling program and erase | Hsiang-Lan Lung, Yen-Hao Shih, Erh-Kun Lai, Ming-Hsiu Lee | 2013-04-23 |
| 8383512 | Method for making multilayer connection structure | Shih-Hung Chen, Hong-Ji Lee, Chin-Cheng Yang | 2013-02-26 |
| 8378410 | Semiconductor device and method of manufacturing the same | Sheng-Chih Lai | 2013-02-19 |
| 8362615 | Memory and manufacturing method thereof | Erh-Kun Lai, Kuang Yeu Hsieh | 2013-01-29 |
| 8363476 | Memory device, manufacturing method and operating method of the same | Shih-Hung Chen | 2013-01-29 |
| 8343840 | Blocking dielectric engineered charge trapping memory cell with high speed erase | Sheng-Chih Lai, Chien-Wei Liao | 2013-01-01 |
| 8330210 | High-κ capped blocking dielectric bandgap engineered SONOS and MONOS | Sheng-Chih Lai, Chien-Wei Liao | 2012-12-11 |
| 8325530 | Cell operation methods using gate-injection for floating gate NAND flash memory | Tzu-Hsuan Hsu, Erh-Kun Lai | 2012-12-04 |
| 8324681 | Stacked non-volatile memory device and methods for fabricating the same | Erh-Kun Lai, Kuang Yeu Hsieh | 2012-12-04 |
| 8315095 | Multi-gate bandgap engineered memory | Szu-Yu Wang | 2012-11-20 |
| 8304911 | Semiconductor structure and manufacturing method of the same | Shih-Hung Chen, Yi-Hsuan Hsiao | 2012-11-06 |
| 8288815 | Gate structure of semiconductor device having a conductive structure with a middle portion and two spacer portions | Erh-Kun Lai | 2012-10-16 |
| 8284597 | Diode memory | Kuo-Pin Chang | 2012-10-09 |
| 8264028 | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays | Szu-Yu Wang | 2012-09-11 |