Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11761880 | Process-induced distortion prediction and feedforward and feedback correction of overlay errors | Pradeep Vukkadala, Haiguang Chen, Jaydeep Sinha | 2023-09-19 |
| 10509329 | Breakdown analysis of geometry induced overlay and utilization of breakdown analysis for improved overlay control | Chin-Chou Huang | 2019-12-17 |
| 10401279 | Process-induced distortion prediction and feedforward and feedback correction of overlay errors | Pradeep Vukkadala, Haiguang Chen, Jaydeep Sinha | 2019-09-03 |
| 10379061 | Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool | Haiguang Chen, Jaydeep Sinha, Sergey Kamensky, Pradeep Vukkadala | 2019-08-13 |
| 10249523 | Overlay and semiconductor process control using a wafer geometry metric | Pradeep Vukkadala, Jaydeep Sinha | 2019-04-02 |
| 10025894 | System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking | Pradeep Vukkadala, Jaydeep Sinha, Haiguang Chen, Michael D. Kirk | 2018-07-17 |
| 9865047 | Systems and methods for effective pattern wafer surface measurement and analysis using interferometry tool | Haiguang Chen, Jaydeep Sinha, Enrique Chavez | 2018-01-09 |
| 9558545 | Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry | Pradeep Vukkadala, Soham Dey, Jaydeep Sinha | 2017-01-31 |
| 9546862 | Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool | Haiguang Chen, Jaydeep Sinha, Sergey Kamensky, Pradeep Vukkadala | 2017-01-17 |
| 9513565 | Using wafer geometry to improve scanner correction effectiveness for overlay control | Craig MacNaughton, Pradeep Vukkadala, Jaydeep Sinha, Amir Azordegan | 2016-12-06 |
| 9430593 | System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking | Pradeep Vukkadala, Jaydeep Sinha, Haiguang Chen, Michael D. Kirk | 2016-08-30 |
| 9354526 | Overlay and semiconductor process control using a wafer geometry metric | Pradeep Vukkadala, Jaydeep Sinha | 2016-05-31 |
| 9029810 | Using wafer geometry to improve scanner correction effectiveness for overlay control | Craig MacNaughton, Pradeep Vukkadala, Jaydeep Sinha, Amir Azordegan | 2015-05-12 |
| 8768665 | Site based quantification of substrate topography and its relation to lithography defocus and overlay | Jaydeep Sinha | 2014-07-01 |
| 8065109 | Localized substrate geometry characterization | Jaydeep Sinha, Rabi Fettig | 2011-11-22 |