ZH

Ziyad S. Hakura

NV NVIDIA: 86 patents #12 of 7,811Top 1%
Microsoft: 1 patents #24,826 of 40,388Top 65%
Overall (All Time): #19,234 of 4,157,543Top 1%
87
Patents All Time

Issued Patents All Time

Showing 1–25 of 87 patents

Patent #TitleCo-InventorsDate
11663767 Power efficient attribute handling for tessellation and geometry shaders Dale L. Kirkland 2023-05-30
11468630 Rendering scenes using a combination of raytracing and rasterization Christoph Kubisch, Manuel Kraemer 2022-10-11
11107176 Scheduling cache traffic in a tile-based architecture Rouslan Dimitrov 2021-08-31
11016802 Techniques for ordering atomic operations Olivier Giroux, Wishwesh Anil Gandhi 2021-05-25
10909739 Techniques for representing and processing geometry within an expanded graphics processing pipeline Yury Uralsky, Christoph Kubisch, Pierre Boudier, Henry Packard Moreton 2021-02-02
10878611 Techniques for pre-processing index buffers for a graphics processing pipeline Yury Uralsky, Christoph Kubisch, Pierre Boudier, Henry Packard Moreton 2020-12-29
10861230 System-generated stable barycentric coordinates and direct plane equation access David Patrick, Dale L. Kirkland, Henry Packard Moreton, Yury Uralsky 2020-12-08
10853994 Rendering scenes using a combination of raytracing and rasterization Christoph Kubisch, Manuel Kraemer 2020-12-01
10600229 Techniques for representing and processing geometry within a graphics processing pipeline Yury Uralsky, Christoph Kubisch, Pierre Boudier, Henry Packard Moreton 2020-03-24
10489875 Data structures for efficient tiled rendering Cynthia Ann Edgeworth Allison 2019-11-26
10453168 Techniques for maintaining atomicity and ordering for pixel shader operations Eric B. Lum, Dale L. Kirkland, Jack Choquette, Patrick R. Brown, Yury Uralsky +1 more 2019-10-22
10438314 Two-pass cache tile processing for visibility testing in a tile-based architecture Jerome F. Duluk, Jr. 2019-10-08
10430989 Multi-pass rendering in a screen space pipeline Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Jeffrey A. Bolz, Yury Uralsky, Jonah M. Alben 2019-10-01
10332310 Distributed index fetch, primitive assembly, and primitive batching Niket Agrawal, Amit Jain, Dale L. Kirkland, Karim M. Abdalla, Haren Kethareswaran 2019-06-25
10282803 State handling in a tiled architecture Pierre Souillot, Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Walter R. Steiner 2019-05-07
10223122 Managing event count reports in a tile-based architecture Jerome F. Duluk, Jr. 2019-03-05
10147222 Multi-pass rendering in a screen space pipeline Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Jeffrey A. Bolz, Yury Uralsky, Jonah M. Alben 2018-12-04
10120187 Sub-frame scanout for latency reduction in virtual reality applications Craig M. Wittenbrink 2018-11-06
10083036 Techniques for managing graphics processing resources in a tile-based architecture Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Andrei Khodakovsky, Jeffrey A. Bolz 2018-09-25
10078911 System, method, and computer program product for executing processes involving at least one primitive in a graphics processor, utilizing a data structure Yury Uralsky, Tyson J. Bergland, Eric B. Lum, Jerome F. Duluk, Jr., Henry Packard Moreton 2018-09-18
10068366 Stereo multi-projection implemented using a graphics processing pipeline Eric B. Lum, Henry Packard Moreton, Emmett M. Kilgariff 2018-09-04
10055806 Techniques for maintaining atomicity and ordering for pixel shader operations Eric B. Lum, Dale L. Kirkland, Jack Choquette, Patrick R. Brown, Yury Uralsky +1 more 2018-08-21
10032242 Managing deferred contexts in a cache tiling architecture Jeffrey A. Bolz, Amanpreet Grewal, Matthew Vernon Johnson, Andrei Khodakovsky 2018-07-24
10032245 Techniques for maintaining atomicity and ordering for pixel shader operations Eric B. Lum, Dale L. Kirkland, Jack Choquette, Patrick R. Brown, Yury Uralsky +1 more 2018-07-24
10032243 Distributed tiled caching Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Walter R. Steiner 2018-07-24