Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12362773 | Integrated programmable gain amplifier (PGA) and protection circuit | Xiaochen Yang, Hamid Hatamkhani, Guansheng Li, Delong Cui, Jun Cao | 2025-07-15 |
| 12348239 | Split-dithering scheme in successive approximation analog to digital converter | Wei Zhang, Jun Cao | 2025-07-01 |
| 12212335 | Reference-ripple compensation technique for SAR ADC | Xin Meng, Jun Cao | 2025-01-28 |
| 11929756 | System and method for offset calibration in a successive approximation analog to digital converter | Jun Cao, Delong Cui | 2024-03-12 |
| 10903846 | Power efficient successive approximation analog to digital converter | Delong Cui, Jun Cao | 2021-01-26 |
| 10810487 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Dharmendra S. Modha +4 more | 2020-10-20 |
| 10628732 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Dharmendra S. Modha +4 more | 2020-04-21 |
| 10541679 | Pulse amplifier | Chang-Shun Liu, Delong Cui, Jun Cao | 2020-01-21 |
| 9660660 | Analog to digital converter with high precision offset calibrated integrating comparators | Troy J. Beukema, Sergey V. Rylov, Mihai A. Sanduleanu, Zeynep Toprak Deniz | 2017-05-23 |
| 9571115 | Analog to digital converter with high precision offset calibrated integrating comparators | Troy J. Beukema, Sergey V. Rylov, Mihai A. Sanduleanu, Zeynep Toprak Deniz | 2017-02-14 |
| 9467313 | Continuous-time linear equalizer for high-speed receiving unit | John F. Bulzacchelli, Pier Andrea Francese, Thomas H. Toifl | 2016-10-11 |
| 9460383 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Dharmendra S. Modha +4 more | 2016-10-04 |
| 9288085 | Continuous-time linear equalizer for high-speed receiving unit | John F. Bulzacchelli, Pier Andrea Francese, Thomas H. Toifl | 2016-03-15 |
| 9240789 | Sub-rate low-swing data receiver | Daniel J. Friedman, Jose A. Tierno | 2016-01-19 |
| 9231603 | Distributed phase detection for clock synchronization in multi-layer 3D stacks | Liang Pang, Phillip J. Restle | 2016-01-05 |
| 9207695 | Calibration schemes for charge-recycling stacked voltage domains | Daniel J. Friedman, Jose A. Tierno | 2015-12-08 |
| 9154159 | Low latency data deserializer | — | 2015-10-06 |
| 8898097 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Dharmendra S. Modha +4 more | 2014-11-25 |
| 8881075 | Method for measuring assertion density in a system of verifying integrated circuit design | Yuan Lu, Nitin Mhaske | 2014-11-04 |
| 8856055 | Reconfigurable and customizable general-purpose circuits for neural networks | Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Dharmendra S. Modha +4 more | 2014-10-07 |
| 8824218 | Compact low-power asynchronous resistor-based memory read operation and circuit | Seongwon Kim, Bipin Rajendran | 2014-09-02 |
| 8809995 | Through silicon via noise suppression using buried interface contacts | Xiaomin Duan, Xiaoxiong Gu, Joel A. Silberman | 2014-08-19 |
| 8797084 | Calibration schemes for charge-recycling stacked voltage domains | Daniel J. Friedman, Jose A. Tierno | 2014-08-05 |
| 8774228 | Timing recovery method and apparatus for an input/output bus with link redundancy | John F. Bulzacchelli, Timothy O. Dickson, Daniel J. Friedman, Sergey V. Rylov | 2014-07-08 |
| 8564340 | Dual phase-locked loop circuit and method for controlling the same | Wen cai Lu, Sterling Smith | 2013-10-22 |