Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10216217 | Adaptive compilation and execution for hardware acceleration | Sonal Santan, Sudipto Chakraborty, Fei Rui, Stephen P. Rozum, Yenpang Lin +1 more | 2019-02-26 |
| 10108769 | Delay modeling for high fan-out nets within circuit designs | Grigor S. Gasparyan | 2018-10-23 |
| 8972920 | Re-budgeting connections of a circuit design | Grigor S. Gasparyan, Dinesh D. Gaitonde | 2015-03-03 |
| 8769461 | Replicating a driver of a net in a circuit design | Anup Kumar Sultania, E. Syama Sundara Reddy | 2014-07-01 |
| 7886256 | Timing analysis of a mapped logic design using physical delays | Pradip K. Jha, Dinesh D. Gaitonde | 2011-02-08 |
| 6286128 | Method for design optimization using logical and physical information | Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li +17 more | 2001-09-04 |