Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11544214 | Monolithic vector processor configured to operate on variable length vectors using a vector length register | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2023-01-03 |
| 10922267 | Vector processor to operate on variable length vectors using graphics processing instructions | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Sitij Agrawal | 2021-02-16 |
| 10339094 | Vector processor configured to operate on variable length vectors with asymmetric multi-threading | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2019-07-02 |
| 10339095 | Vector processor configured to operate on variable length vectors using digital signal processing instructions | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2019-07-02 |
| 9959246 | Vector processor configured to operate on variable length vectors using implicitly typed instructions | Mayan Moudgill, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley | 2018-05-01 |
| 9766894 | Method and apparatus for enabling a processor to generate pipeline control signals | C. John Glossner, Gary J. Nacer, Murugappan Senthilvelan, Arthur Joseph Hoane, Paul D'Arcy +2 more | 2017-09-19 |
| 9558000 | Multithreading using an ordered list of hardware contexts | C. John Glossner, Gary J. Nacer, Murugappan Senthilvelan, Arthur Joseph Hoane, Paul D'Arcy +2 more | 2017-01-31 |
| 8539188 | Method for enabling multi-processor synchronization | Mayan Moudgill, Murugappan Senthilvelan, Umesh Srikantiah, Tak-po Li, Pablo Balzola | 2013-09-17 |