Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11961575 | Single “A” latch with an array of “B” latches | Thomas A. Ziaja, Dinesh R. AMIRTHARAJ | 2024-04-16 |
| 11443822 | Method and circuit for row scannable latch array | Thomas A. Ziaja, Dinesh R. AMIRTHARAJ | 2022-09-13 |
| 11443823 | Method and circuit for scan dump of latch array | Thomas A. Ziaja, Dinesh R. AMIRTHARAJ | 2022-09-13 |
| 10169264 | Implementing robust readback capture in a programmable integrated circuit | Michelle Zeng, Subodh Kumar, Weiguang Lu, Karthy Rajasekharan, Kumar Rahul | 2019-01-01 |
| 10110234 | Efficient system debug infrastructure for tiled architecture | Subodh Kumar, Adam Elkins, Ghazaleh Mirjafari, Amitava Majumdar | 2018-10-23 |
| 10108376 | Memory initialization | Michelle Zeng, Subodh Kumar, Weiguang Lu, Hsiao-Hui Chen | 2018-10-23 |
| 9075930 | Configurable embedded memory system | Subodh Kumar, James M. Simkins, Thomas H. Strader, Matthew H. Klein, James E. Ogden | 2015-07-07 |
| 9018980 | Bimodal clock generator | Subodh Kumar, Michelle Zeng, Hsiao-Hui Chen | 2015-04-28 |
| 8912829 | Method and apparatus for using a synchronous reset pulse to reset circuitry in multiple clock domains | James E. Ogden, James M. Simkins, Subodh Kumar | 2014-12-16 |
| 8130587 | Efficient method of replicate memory data with virtual port solution | Zhen Liu, Kenway Tam | 2012-03-06 |