| 8549452 |
Method for supporting multiple libraries characterized at different process, voltage and temperature points |
Revanta Banerji, Peter Feldmann, Hemlata Gupta |
2013-10-01 |
| 8515725 |
Characterization of nonlinear cell macro model for timing analysis |
Peter Feldmann, Sampath Dechu, Ratan Singh |
2013-08-20 |
| 8463571 |
Performing reliability analysis of signal wires |
Ayesha Akhter, Peter Feldmann, Joachim Keinert |
2013-06-11 |
| 8396910 |
Efficient compression and handling of model library waveforms |
Peter Feldmann, Safar Hatami |
2013-03-12 |
| 8359563 |
Moment-based characterization waveform for static timing analysis |
Peter Feldmann, David Ling, Chandramouli Visweswariah |
2013-01-22 |
| 8239810 |
Method and system for optimizing a device with current source models |
Peter Feldmann, Peter A. Habitz, Safar Hatami |
2012-08-07 |
| 8122411 |
Method of performing static timing analysis considering abstracted cell's interconnect parasitics |
Debjit Sinha |
2012-02-21 |
| 8108815 |
Order independent method of performing statistical N-way maximum/minimum operation for non-Gaussian and non-linear distributions |
Peter Feldmann |
2012-01-31 |
| 8103997 |
Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits |
Debjit Sinha, Adil Bhanji, Jeffrey M. Ritzinger |
2012-01-24 |
| 8020129 |
Multiple voltage threshold timing analysis for a digital integrated circuit |
Peter Feldmann |
2011-09-13 |
| 7941775 |
Arbitrary waveform propagation through a logic gate using timing analysis results |
Peter Feldmann |
2011-05-10 |
| 7814448 |
Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits |
David J. Hathaway, Chandramouli Visweswariah, Jinjun Xiong, Vladimir Zolotov |
2010-10-12 |
| 7788617 |
Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis |
Adil Bhanji, Peter Feldmann, Debjit Sinha |
2010-08-31 |
| 7739640 |
Method and apparatus for static timing analysis in the presence of a coupling event and process variation |
Gregory M. Schaeffer, Chandramouli Visweswariah |
2010-06-15 |
| 7685549 |
Method of constrained aggressor set selection for crosstalk induced noise |
Debjit Sinha, Ayesha Akhter, Gregory M. Schaeffer, David J. Widiger |
2010-03-23 |
| 7594209 |
Method for incorporating Miller capacitance effects in digital circuits for an accurate timing analysis |
Harry J. Beatty, III |
2009-09-22 |
| 7552412 |
Integrated circuit (IC) chip design method, program product and system |
Gary S. Ditlow, Chandramouli V. Kashyap, Ruchir Puri |
2009-06-23 |
