Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411778 | Advanced initialization bus (AIB) | Danh La | 2025-09-09 |
| 12314130 | Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization | Massimo Sutera, Nagi Aboulenein | 2025-05-27 |
| 12282064 | Component die validation built-in self-test (VBIST) engine | Jared Eric Bendt, Nagi Aboulenein, Kedar KARANDIKAR, Stephan Jourdan | 2025-04-22 |
| 12204410 | Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilization | Massimo Sutera, Nagi Aboulenein | 2025-01-21 |
| 12159056 | Extending functionality of memory controllers in a processor-based device | Massimo Sutera, Nagi Aboulenein, Brian Thomas Chase, James Edward Casteel, Kha Minh Huynh +1 more | 2024-12-03 |
| 12019565 | Advanced initialization bus (AIB) | Danh La | 2024-06-25 |
| 11934263 | Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization | Massimo Sutera, Nagi Aboulenein | 2024-03-19 |
| 11868209 | Method and system for sequencing data checks in a packet | Matthew Robert Erler, Robert J. Safranek, Robert J. Toepfer, Shailendra Ramrao Chavan, Jonglih Yu | 2024-01-09 |
| 11481270 | Method and system for sequencing data checks in a packet | Matthew Robert Erler, Robert J. Safranek, Robert J. Toepfer, Shailendra Ramrao Chavan, Jonglih Yu | 2022-10-25 |
| 10885952 | Memory data transfer and switching sequence | Takashi Ueda, Jeffrey Earl, Utpal Mahanta | 2021-01-05 |
| 10545866 | Method and system for efficient re-determination of a data valid window | Yoshiharu Kato, Manas Lahon | 2020-01-28 |
| 9886987 | System and method for data-mask training in non-provisioned random access memory | Jeffrey Earl | 2018-02-06 |
| 9811273 | System and method for reliable high-speed data transfer in multiple data rate nonvolatile memory | — | 2017-11-07 |
| 9471094 | Method of aligning timing of a chip select signal with a cycle of a memory device | Jeffrey Earl, Todd Barth | 2016-10-18 |
| 9159423 | Robust erase page detection logic for NAND flash memory devices | Srinivas Suresh Revankar | 2015-10-13 |
| 8904082 | Operation based polling in a memory system | Bikram Banerjee | 2014-12-02 |
| 8880980 | System and method for expeditious transfer of data from source to destination in error corrected manner | Anish Mathew, Raveendra Pai G. | 2014-11-04 |
| 8812898 | System and method for transfer of data between memory with dynamic error recovery | Manas Lahon | 2014-08-19 |
| 7941587 | Programmable sequence generator for a flash memory controller | Anish Mathew, Bikram Banerjee | 2011-05-10 |
| 7739557 | Method, system and program product for autonomous error recovery for memory devices | Tin-Chee Lo, Jeffrey M. Turner | 2010-06-15 |
| 7275202 | Method, system and program product for autonomous error recovery for memory devices | Tin-Chee Lo, Jeffrey M. Turner | 2007-09-25 |