TB

Todd Barth

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
Overall (All Time): #3,022,787 of 4,157,543Top 75%
1
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9471094 Method of aligning timing of a chip select signal with a cycle of a memory device Sandeep Brahmadathan, Jeffrey Earl 2016-10-18