RP

Robert J. Palermo

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
UN Unisys: 3 patents #459 of 2,015Top 25%
SA Siemens Energy & Automation: 2 patents #136 of 424Top 35%
Overall (All Time): #581,497 of 4,157,543Top 15%
9
Patents All Time

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDate
7647220 Transistor-level timing analysis using embedded simulation Pawan Kulshreshtha, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin 2010-01-12
6877143 System and method for timing abstraction of digital logic circuits Karem A. Sakallah, Shekaripuram V. Venkatesh, Mohammad Mortazavi 2005-04-05
6760894 Method and mechanism for performing improved timing analysis on virtual component blocks Hakan Yalcin, Cyrus Bamji, Mohammad Mortazavi 2004-07-06
6442739 System and method for timing abstraction of digital logic circuits Karem A. Sakallah, Shekaripuram V. Venkatesh, Mohammad Mortazavi 2002-08-27
5831869 Method of compacting data representations of hierarchical logic designs used for static timing analysis Clive Robert Ellis 1998-11-03
5765000 Dynamic user interrupt scheme in a programmable logic controller Ronald Mitchell, Mark Steven Boggs, Temple L. Fulton 1998-06-09
5761097 Logic timing analysis for multiple-clock designs 1998-06-02
5724250 Method and apparatus for performing drive strength adjust optimization in a circuit design Joseph P. Kerzman, Kenneth L. Engelbrecht, Douglas A. Fuller 1998-03-03
5594917 High speed programmable logic controller Alan D. McNutt, Daniel F. Moon 1997-01-14