KS

Karem A. Sakallah

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
University of Michigan: 3 patents #689 of 4,352Top 20%
📍 Ann Arbor, MI: #1,235 of 6,071 inventorsTop 25%
🗺 Michigan: #13,574 of 86,293 inventorsTop 20%
Overall (All Time): #735,886 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
9389983 Verification of complex systems that can be described by a finite state transition system Suho LEE 2016-07-12
8954909 Automated scalable verification for hardware designs at the register transfer level Zaher Andraus, Mark Liffiton 2015-02-10
8601414 Automated scalable verification for hardware designs at the register transfer level Zaher Andraus, Mark Liffiton 2013-12-03
7346872 Functional timing analysis for characterization of virtual component blocks Hakan Yalcin, Robert J. Palmero, Mohammad Mortazavi, Cyrus Bamji 2008-03-18
6877143 System and method for timing abstraction of digital logic circuits Robert J. Palermo, Shekaripuram V. Venkatesh, Mohammad Mortazavi 2005-04-05
6457159 Functional timing analysis for characterization of virtual component blocks Hakan Yalcin, Robert J. Palmero, Mohammad Mortazavi, Cyrus Bamji 2002-09-24
6442739 System and method for timing abstraction of digital logic circuits Robert J. Palermo, Shekaripuram V. Venkatesh, Mohammad Mortazavi 2002-08-27