Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10747794 | Smart search for annotations and inking | Nithin Raj M, Neha Motghare | 2020-08-18 |
| 10630755 | Selective consumption of web page data over a data-limited connection | Deepak Agrawal, Bibhu Choudhary, Nithin Ismail, Saurabh Satnalika, Nithin Raj M | 2020-04-21 |
| 10102194 | Shared knowledge about contents | Arindam Biswas, Saloni Agarwal, Gowthami Chegu, Bibhu Choudhary, Arif Alam Siddique | 2018-10-16 |
| 7039887 | Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques | Nadim Khalil, Stuart Rae, David John Roberts | 2006-05-02 |
| 6714902 | Method and apparatus for critical and false path verification | Han-Hsun Chao, Alexander Saldanha | 2004-03-30 |
| 6651144 | Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state | James B. Keller, Richard E. Kessler | 2003-11-18 |
| 6493802 | Method and apparatus for performing speculative memory fills into a microprocessor | James B. Keller, Richard E. Kessler | 2002-12-10 |
| 6463523 | Method and apparatus for delaying the execution of dependent loads | Richard E. Kessler, Edward J. McLellan | 2002-10-08 |
| 6446143 | Methods and apparatus for minimizing the impact of excessive instruction retrieval | Edward J. McLellan | 2002-09-03 |
| 6401173 | Method and apparatus for optimizing bcache tag performance by inferring bcache tag state from internal processor state | David A. Webb, James B. Keller | 2002-06-04 |
| 6397302 | Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system | James B. Keller, Richard E. Kessler | 2002-05-28 |
| 6349366 | Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commands | James B. Keller, Richard E. Kessler | 2002-02-19 |
| 6314496 | Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commands | James B. Keller, Richard E. Kessler | 2001-11-06 |
| 6295583 | Method and apparatus for resolving probes in multi-processor systems which do not use external duplicate tags for probe filtering | Solomon J. Katzman, James B. Keller, Richard E. Kessler | 2001-09-25 |
| 6253285 | Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processing | Richard E. Kessler, James B. Keller | 2001-06-26 |
| 6253301 | Method and apparatus for a dedicated physically indexed copy of the data cache tag arrays | David A. Webb, James B. Keller, Derrick R. Meyer | 2001-06-26 |
| 6249846 | Distributed data dependency stall mechanism | Stephen R. Van Doren | 2001-06-19 |
| 6199153 | Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements | Solomon J. Katzman, James B. Keller, Richard E. Kessler | 2001-03-06 |
| 6141734 | Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol | David A. Webb, James B. Keller, Derrick R. Meyer, Daniel Leibholz | 2000-10-31 |
| 6085294 | Distributed data dependency stall mechanism | Stephen R. Van Doren | 2000-07-04 |
| 6035123 | Determining hardware complexity of software operations | Michael D. Smith | 2000-03-07 |
| 5924120 | Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times | David A. Webb, James B. Keller, Derrick R. Meyer | 1999-07-13 |
| 5819064 | Hardware extraction technique for programmable reduced instruction set computers | Michael D. Smith | 1998-10-06 |
| 5696956 | Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents | Bill Grundmann, Michael D. Smith | 1997-12-09 |
| 5694579 | Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation | Gabriel Bischoff | 1997-12-02 |