| 9697899 |
Parallel deflate decoding method and apparatus |
Lokpraveen Mosur, Sailesh Bissessur, Pradnyesh S. Gudadhe |
2017-07-04 |
| 8766827 |
Parallel apparatus for high-speed, highly compressed LZ77 tokenization and Huffman encoding for deflate compression |
Andrew Milne, Sailesh Bissessur, Lokpraveen Mosur |
2014-07-01 |
| 8373583 |
Compression producing output exhibiting compression ratio that is at least equal to desired compression ratio |
Lokpraveen Mosur, Sailesh Bissessur, Prashant Paliwal, Andrew Milne |
2013-02-12 |
| 7694080 |
Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput |
R. Frank O'Bleness, Sujat Jamil, Hang T. Nguyen |
2010-04-06 |
| 7487398 |
Microprocessor design support for computer system and platform validation |
Ayman G. Abdo, Cameron McNairy, Piyush Desai |
2009-02-03 |
| 7194671 |
Mechanism handling race conditions in FRC-enabled processors |
Steven Tu, Alexander J. Honcharik, Hang T. Nguyen, Sujat Jamil |
2007-03-20 |
| 7120755 |
Transfer of cache lines on-chip between processing cores in a multi-core system |
Sujat Jamil, Cameron McNairy |
2006-10-10 |
| 7032134 |
Microprocessor design support for computer system and platform validation |
Ayman G. Abdo, Cameron McNairy, Piyush Desai |
2006-04-18 |
| 7003632 |
Method and apparatus for scalable disambiguated coherence in shared storage hierarchies |
Sujat Jamil, Hang T. Nguyen |
2006-02-21 |
| 6651145 |
Method and apparatus for scalable disambiguated coherence in shared storage hierarchies |
Sujat Jamil, Hang T. Nguyen |
2003-11-18 |
| 5829038 |
Backward inquiry to lower level caches prior to the eviction of a modified line from a higher level cache in a microprocessor hierarchical cache structure |
Wen-Hann Wang |
1998-10-27 |
| 5787469 |
System and method for exclusively writing tag during write allocate requests |
— |
1998-07-28 |