Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8735980 | Configuration and fabrication of semiconductor structure using empty and filled wells | Constantin Bulucea, Sandeep R. Bahl, William French, Jeng-Jiun Yang, Donald M. Archer +1 more | 2014-05-27 |
| 8673720 | Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile | D. Courtney Parker | 2014-03-18 |
| 8304835 | Configuration and fabrication of semiconductor structure using empty and filled wells | Constantin Bulucea, Sandeep R. Bahl, William French, Jeng-Jiun Yang, Donald M. Archer +1 more | 2012-11-06 |
| 8253208 | Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile | D. Courtney Parker | 2012-08-28 |
| 8129262 | Fabrication of field-effect transistor with vertical body-material dopant profile tailored to alleviate punchthrough and reduce current leakage | Constantin Bulucea, Fu-Cheng Wang | 2012-03-06 |
| 7879669 | Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length | Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang | 2011-02-01 |
| 7785971 | Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage | Constantin Bulucea, Fu-Cheng Wang | 2010-08-31 |
| 7718448 | Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays | Douglas Brisbin | 2010-05-18 |
| 7700980 | Structure and fabrication of field-effect transistor for alleviating short-channel effects | Constantin Bulucea, Fu-Cheng Wang | 2010-04-20 |
| 7701005 | Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics | Constantin Bulucea, Fu-Cheng Wang | 2010-04-20 |
| 7645657 | MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation | Douglas Brisbin, Denis Finbarr O'Connell, Heather McCulloh, Sergei Drizlikh | 2010-01-12 |
| 7595244 | Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics | Constantin Bulucea, Fu-Cheng Wang | 2009-09-29 |
| 7390682 | Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level | Barry O'Connell, Jonggook Kim | 2008-06-24 |
| 7170090 | Method and structure for testing metal-insulator-metal capacitor structures under high temperature at wafer level | Barry O'Connell, Jonggook Kim | 2007-01-30 |
| 7145191 | P-channel field-effect transistor with reduced junction capacitance | Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang | 2006-12-05 |
| 6927474 | Method of programming an antifuse | Denis Finbarr O'Connell | 2005-08-09 |
| 6797555 | Direct implantation of fluorine into the channel region of a PMOS device | Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko | 2004-09-28 |
| 6797576 | Fabrication of p-channel field-effect transistor for reducing junction capacitance | Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang | 2004-09-28 |
| 6599804 | Fabrication of field-effect transistor for alleviating short-channel effects | Constantin Bulucea, Fu-Cheng Wang | 2003-07-29 |
| 6548842 | Field-effect transistor for alleviating short-channel effects | Constantin Bulucea, Fu-Cheng Wang | 2003-04-15 |