Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9418856 | Methods of forming titanium-aluminum layers for gate electrodes and related semiconductor devices | Clint E. Bordelon, David Williams, Jun Han Kim | 2016-08-16 |
| 8481142 | System and method for monitoring chloride content and concentration induced by a metal etch process | Thanas Budri, Thomas Francis, David Tucker, Stephen W. Swan | 2013-07-09 |
| 8471369 | Method and apparatus for reducing plasma process induced damage in integrated circuits | Heather McCulloh, Denis Finbarr O'Connell, Douglas Brisbin | 2013-06-25 |
| 7915093 | System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process | Ashish Kushwaha, Thomas James Moutinho, David Tucker | 2011-03-29 |
| 7645657 | MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation | Douglas Brisbin, Prasad Chaparala, Denis Finbarr O'Connell, Heather McCulloh | 2010-01-12 |
| 7531896 | Semiconductor device having a minimal via resistance created by applying a nitrogen plasma to a titanium via liner | Thomas Francis | 2009-05-12 |
| 7504340 | System and method for providing contact etch selectivity using RIE lag dependence on contact aspect ratio | Thomas Francis, Lee James Jacobson | 2009-03-17 |
| 7247544 | High Q inductor integration | Todd Thibeault, Thomas Francis | 2007-07-24 |
| 7229908 | System and method for manufacturing an out of plane integrated circuit inductor | Todd Thibeault | 2007-06-12 |
| 7101787 | System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition | Thomas Francis | 2006-09-05 |