Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12050910 | Device and method for hardware-efficient adaptive calculation of floating-point trigonometric functions using coordinate rotate digital computer (CORDIC) | Mayan Moudgill, Murugappan Senthivelan, Vaidyanathan Ramdurai, Sitij Agrawal | 2024-07-30 |
| 11928465 | Device and method for calculating elementary functions using successive cumulative rotation circuit | Mayan Moudgill, Murugappan Senthivelan, Vaidyanathan Ramdurai, Sitij Agrawal | 2024-03-12 |
| 11544214 | Monolithic vector processor configured to operate on variable length vectors using a vector length register | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2023-01-03 |
| 10846259 | Vector processor to operate on variable length vectors with out-of-order execution | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Murugappan Senthilvelan | 2020-11-24 |
| 10514915 | Computer processor with address register file | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley +1 more | 2019-12-24 |
| 10339094 | Vector processor configured to operate on variable length vectors with asymmetric multi-threading | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2019-07-02 |
| 10339095 | Vector processor configured to operate on variable length vectors using digital signal processing instructions | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2019-07-02 |
| 10169039 | Computer processor that implements pre-translation of virtual addresses | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley +1 more | 2019-01-01 |
| 9940129 | Computer processor with register direct branches and employing an instruction preload structure | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley +1 more | 2018-04-10 |
| 9910824 | Vector processor configured to operate on variable length vectors using instructions to combine and split vectors | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +1 more | 2018-03-06 |
| 9792116 | Computer processor that implements pre-translation of virtual addresses with target registers | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley +1 more | 2017-10-17 |
| 8539188 | Method for enabling multi-processor synchronization | Mayan Moudgill, Vitaly Kalashnikov, Murugappan Senthilvelan, Umesh Srikantiah, Tak-po Li | 2013-09-17 |
| 7593978 | Processor reduction unit for accumulation of multiple operands with or without saturation | Michael Schulte, C. John Glossner | 2009-09-22 |
| 7428567 | Arithmetic unit for addition or subtraction with preliminary saturation detection | Michael Schulte, Erdem Hokenek, C. John Glossner | 2008-09-23 |