Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423504 | Adaptive path based analysis process | Umesh Gupta, Marut Agarwal, Satyendra Patel, Prashant Sethia, Ankit Sethi +1 more | 2025-09-23 |
| 12392843 | System and method for managing a battery pack | Sundaraaman K. V., Narayan Surendra Mahipati, Tanishq Choudhary, Sudharshan Reddy Godi, Krishna Prasad TL +1 more | 2025-08-19 |
| 12332304 | System and method for automatic fault detection in an electronic design | Sushobhit Singh, Arvind Nembili Veeravalli, Mahesh D. Sadhankar, Daksh Bakshi | 2025-06-17 |
| 12321583 | Systems and methods for artificial intelligence (AI)-driven data mapping user-interface (UI) generation | Roman Cwalina, Manish Pandey, Namithanath Padayath, Samuel T. Bielaczyc, John Moriarty +4 more | 2025-06-03 |
| 12277101 | Dataframe workloads using read-only data snapshots | Srilakshmi Chintala, Jianzhun Du, Srinath Shankar, Leonhard Franz Spiegelberg, Eric Vandenberg +2 more | 2025-04-15 |
| 12216648 | Row-order dependent dataframe workloads | Srilakshmi Chintala, Jianzhun Du, Srinath Shankar, Leonhard Franz Spiegelberg, Eric Vandenberg +2 more | 2025-02-04 |
| 12041053 | Granular SaaS tenant restriction systems and methods | Pooja Deshmukh, Narinder Paul, Santhosh Kumar, Sravani Manukonda, Vijay Bulusu | 2024-07-16 |
| 12038887 | Low-latency database analysis using external data sources | Siva Singaram, Rakesh Kothari, Jasmeet Singh Jaggi, Rahul Manikanta Balakavi, Tushar Mahale +2 more | 2024-07-16 |
| 11971765 | Dynamic network-wide coordinated management of power over ethernet | Yashavantha Nagaraju Naguvanahalli, Vigneshwara Upadhyaya, Isaac Theogaraj | 2024-04-30 |
| 11544239 | Low-latency database analysis using external data sources | Sandeep Kumar, Siva Singaram, Rakesh Kothari, Jasmeet Singh Jaggi, Manikanta Balakavi +2 more | 2023-01-03 |
| 11531803 | IPBA-driven full-depth EPBA of operational timing for circuit design | Umesh Gupta, Marut Agarwal, Rakesh Agarwal | 2022-12-20 |
| 11514218 | System and method for performing static timing analysis of electronic circuit designs using a tag-based approach | Hemendra Singh Negi, Arunjai Singh | 2022-11-29 |
| 11455450 | System and method for performing sign-off timing analysis of electronic circuit designs | Sushobhit Singh, Arvind Nembili Veeravalli, Beenish, Mahesh D. Sadhankar, Ankit Sethi | 2022-09-27 |
| 11416477 | Systems and methods for database analysis | Satyam Shekhar, Nitish Rajguru, Mayank Raj, Priyendra Singh Deshwal | 2022-08-16 |
| 11347915 | System and method for objective probing and generation of timing constraints associated with an electronic circuit design | Sushobhit Singh, Puneet Munjal | 2022-05-31 |
| 11343247 | Local delegation of remote key management service | Anand Ozarkar, Imam Sheikh | 2022-05-24 |
| 10915685 | Circuit stage credit based approaches to static timing analysis of integrated circuits | Umesh Gupta, Rakesh Agarwal, Sukriti Khanna, Jayant Sharma, Ritika Govila | 2021-02-09 |
| 10783300 | Systems and methods for extracting hierarchical path exception timing models | Sushobhit Singh, Beenish, Ankur Gulati, Vishal Karda, Shashank Rajendra Prasad | 2020-09-22 |
| 10776547 | Infinite-depth path-based analysis of operational timing for circuit design | Umesh Gupta, Prashant Sethia, Ritika Govila, Jayant Sharma | 2020-09-15 |
| 10686904 | System and method for pushing smart alerts | — | 2020-06-16 |
| 10594871 | Automated bulk provisioning of primary rate interface and SIP trunk telephone numbers | Prasanna Nagaraj, Srinivas Guduru | 2020-03-17 |
| 10516579 | Techniques for reconciliation of planned network with deployed network | Jayaram Hanumanthappa, Naresh Srinivasulu Jayam, Arijit Mandal, Gounda Mohammed Nabi Saheb, Alok Jain +1 more | 2019-12-24 |
| 10255403 | Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs | Sneh Saurabh | 2019-04-09 |
| 10114920 | Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic | Umesh Gupta, Shashank Tripathi, Arvind Nembili Veeravalli, Prashant Sethia, Ritika Govila | 2018-10-30 |
| 9875333 | Comprehensive path based analysis process | Sourabh Kumar Verma, Ajay Tomar, Rakesh Agarwal, Umesh Gupta, Manish Bansal +2 more | 2018-01-23 |