Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11650817 | System and method to implement masked vector instructions | Mayan Moudgill | 2023-05-16 |
| 11544214 | Monolithic vector processor configured to operate on variable length vectors using a vector length register | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2023-01-03 |
| 10908909 | Processor with mode support | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley | 2021-02-02 |
| 10846259 | Vector processor to operate on variable length vectors with out-of-order execution | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Pablo Balzola | 2020-11-24 |
| 10514915 | Computer processor with address register file | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley +1 more | 2019-12-24 |
| 10339094 | Vector processor configured to operate on variable length vectors with asymmetric multi-threading | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2019-07-02 |
| 10339095 | Vector processor configured to operate on variable length vectors using digital signal processing instructions | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +3 more | 2019-07-02 |
| 10169039 | Computer processor that implements pre-translation of virtual addresses | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley +1 more | 2019-01-01 |
| 9940129 | Computer processor with register direct branches and employing an instruction preload structure | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley +1 more | 2018-04-10 |
| 9910824 | Vector processor configured to operate on variable length vectors using instructions to combine and split vectors | Mayan Moudgill, Gary J. Nacer, C. John Glossner, Arthur Joseph Hoane, Paul Hurtley +1 more | 2018-03-06 |
| 9792116 | Computer processor that implements pre-translation of virtual addresses with target registers | Mayan Moudgill, Gary J. Nacer, C. John Glossner, A. Joseph Hoane, Paul Hurtley +1 more | 2017-10-17 |
| 9766894 | Method and apparatus for enabling a processor to generate pipeline control signals | C. John Glossner, Gary J. Nacer, Vitaly Kalashnikov, Arthur Joseph Hoane, Paul D'Arcy +2 more | 2017-09-19 |
| 9558000 | Multithreading using an ordered list of hardware contexts | C. John Glossner, Gary J. Nacer, Vitaly Kalashnikov, Arthur Joseph Hoane, Paul D'Arcy +2 more | 2017-01-31 |
| 8539188 | Method for enabling multi-processor synchronization | Mayan Moudgill, Vitaly Kalashnikov, Umesh Srikantiah, Tak-po Li, Pablo Balzola | 2013-09-17 |