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Active power management in a computing device subsystem based on micro-idle duration |
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Refresh timer synchronization between memory controller and memory |
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Systems and methods for individually configuring dynamic random access memories sharing a common command access bus |
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Philip Michael Clovis, Isaac Berk |
2017-07-11 |
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Low latency synchronization scheme for mesochronous DDR system |
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| 9396109 |
Method and apparatus for DRAM spatial coalescing within a single channel |
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2016-07-19 |
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Low latency synchronization scheme for mesochronous DDR system |
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System and method of monitoring a central processing unit in real time |
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Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation |
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2012-01-17 |
| 7437580 |
Dynamic voltage scaling system |
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2008-10-14 |