Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188696 | Method, system, and product for deferred merge based method for graph based analysis pessimism reduction | Amit Dhuria, Sri Harsha POTHUKUCHI, Pradeep Yadav, Pawan Kulshreshtha, Igor Keller +2 more | 2021-11-30 |
| 11144698 | Method, system, and product for an improved approach to placement and optimization in a physical design flow | Vibhor Garg, Edward J. Martinage, Amit Dhuria | 2021-10-12 |
| 10133842 | Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs | Pawan Kulshreshtha, Amit Dhuria, Saulius Kersulis | 2018-11-20 |
| 8788995 | System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design | Naresh Kumar, Prashant Sethia, Amit Dhuria | 2014-07-22 |
| 8745561 | System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design | Vibhor Garg, Pawan Kulshreshtha, Hakan Yalcin | 2014-06-03 |
| 7797649 | Method and system for implementing an analytical wirelength formulation | Hussein Etawil | 2010-09-14 |
| 7356451 | Assertion handling for timing model extraction | Cho Moon, Harish Kriplani | 2008-04-08 |
| 7168053 | Method and system for implementing an analytical wirelength formulation | Hussein Etawil | 2007-01-23 |
| 7107556 | Method and system for implementing an analytical wirelength formulation for unavailability of routing directions | Hussein Etawil, Lu Sha, Jonathan Frankle | 2006-09-12 |
| 6928630 | Timing model extraction by timing graph reduction | Cho Moon, Harish Kriplani | 2005-08-09 |
| 6672776 | Delay estimation for restructuring | Johnson Limqueco, Hong Li, Devadas Varma | 2004-01-06 |
| 6543037 | Delay estimation for restructuring the technology independent circuit | Johnson Limqueco, Hong Li, Devadas Varma | 2003-04-01 |
| 6401231 | Method and apparatus for performing both negative and positive slack time budgeting and for determining a definite required constraint during integrated circuit design | Johnson Limqueco | 2002-06-04 |
| 6023566 | Cluster matching for circuit implementation | Sumit Roy, Devadas Varma | 2000-02-08 |
| 5991524 | Cluster determination for circuit implementation | Sumit Roy, Devadas Varma | 1999-11-23 |
| 5636372 | Network timing analysis method which eliminates timing variations between signals traversing a common circuit path | David J. Hathaway, Janet P. Alvarez | 1997-06-03 |