Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7799598 | Processing systems and methods for molecular memory | Werner G. Kuhr, Ritu Shrivastava, Antonio R. Gallo, Tom DeBolske | 2010-09-21 |
| 7737433 | Electronic junction devices featuring redox electrodes | Richard L. McCreery, Jing Wu | 2010-06-15 |
| 7688662 | Method for hiding a refresh in a pseudo-static memory | — | 2010-03-30 |
| 7533231 | Method and circuit for increasing the memory access speed of an enhanced synchronous memory | Michael T. Peters, Michael A. Schuette | 2009-05-12 |
| 7453752 | Method for hiding a refresh in a pseudo-static memory with plural DRAM sub-arrays and an on-board address decoder | — | 2008-11-18 |
| 7370140 | Enhanced DRAM with embedded registers | Ronald H. Sartore, Donald G. Carrigan, Oscar Frederick Jones, Jr. | 2008-05-06 |
| 7358113 | Processing systems and methods for molecular memory | Ritu Shrivastava, Antonio R. Gallo, Tom DeBolske | 2008-04-15 |
| 7085186 | Method for hiding a refresh in a pseudo-static memory | — | 2006-08-01 |
| 6813679 | Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM | Michael T. Peters, Michael A. Schuette | 2004-11-02 |
| 6538928 | Method for reducing the width of a global data bus in a memory architecture | — | 2003-03-25 |
| 6501698 | Structure and method for hiding DRAM cycle time behind a burst access | — | 2002-12-31 |
| 6347357 | Enhanced DRAM with embedded registers | Ronald H. Sartore, Donald G. Carrigan, Oscar Frederick Jones, Jr. | 2002-02-12 |
| 6330636 | Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank | David Bondurant, Michael T. Peters | 2001-12-11 |
| 6301183 | Enhanced bus turnaround integrated circuit dynamic random access memory device | David Bondurant, David Edward Fisch, Bruce Grieshaber, Michael T. Peters | 2001-10-09 |
| 6289413 | Cached synchronous DRAM architecture having a mode register programmable cache policy | Jim L. Rogers, Steven W. Tomashot, David Bondurant, Oscar Frederick Jones, Jr. | 2001-09-11 |
| 6278646 | Multi-array memory device, and associated method, having shared decoder circuitry | — | 2001-08-21 |
| 6151236 | Enhanced bus turnaround integrated circuit dynamic random access memory device | David Bondurant, David Edward Fisch, Bruce Grieshaber, Michael T. Peters | 2000-11-21 |
| 6141281 | Technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable circuit elements | Steve W. Ash | 2000-10-31 |
| 6064620 | Multi-array memory device, and associated method, having shared decoder circuitry | — | 2000-05-16 |
| 6055192 | Dynamic random access memory word line boost technique employing a boost-on-writes policy | — | 2000-04-25 |
| 5991851 | Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control | Michael Alwais | 1999-11-23 |
| 5887272 | Enhanced DRAM with embedded registers | Ronald H. Sartore, Donald G. Carrigan, Oscar Frederick Jones, Jr. | 1999-03-23 |
| 5721862 | Enhanced DRAM with single row SRAM cache for all device read operations | Ronald H. Sartore, Donald G. Carrigan, Oscar Frederick Jones, Jr. | 1998-02-24 |
| 5699317 | Enhanced DRAM with all reads from on-chip cache and all writers to memory array | Ronald H. Sartore, Donald G. Carrigan, Oscar Frederick Jones, Jr. | 1997-12-16 |
| 5663915 | Amplifier and method for sensing having a pre-bias or coupling step | — | 1997-09-02 |