Ritu Shrivastava — 25 Patents at Alliance Semiconductor

Ritu Shrivastava has been granted 25 US patents while listed as an inventor at Alliance Semiconductor. The first was granted in 1988 and the most recent in April 2023. Ritu Shrivastava ranks #158,593 of 4,157,543 US inventors in our database (top 3.8%). Patent records list Ritu Shrivastava in Fremont, CA, US.

Patents per Year

Issued Patents All Time

Showing 1–25 of 25 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11632365	System and method for smart authentication	Kumar Rao Krishnagi, Kevin Carrier, Vineshkumar Dharmalingam, Ananth Rajasekaran, Najma Aden +6 more	2023-04-18	$533,703,000
8395926	Memory cell with resistance-switching layers and lateral arrangement	Franz Kreupl	2013-03-12	$9,232,000
7799598	Processing systems and methods for molecular memory	Werner G. Kuhr, Antonio R. Gallo, Kenneth J. Mobley, Tom DeBolske	2010-09-21
7642546	Molecular memory devices including solid-state dielectric layers and related methods	Veena Misra, Zhong Chen, Guru Mathur	2010-01-05
7358113	Processing systems and methods for molecular memory	Antonio R. Gallo, Kenneth J. Mobley, Tom DeBolske	2008-04-15
6921688	Method of and apparatus for integrating flash EPROM and SRAM cells on a common substrate	—	2005-07-26	$1,087,000
6903434	Method and apparatus for integrating flash EPROM and SRAM cells on a common substrate	—	2005-06-07	$768,000
6589834	Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current	Chitranjan N. Reddy	2003-07-08	$2,454,000
6472267	DRAM cell having storage capacitor contact self-aligned to bit lines and word lines	Chitranjan N. Reddy	2002-10-29	$1,825,000
6429076	Flash EPROM memory cell having increased capacitive coupling and method of manufacture thereof	Perumal Ratnam	2002-08-06	$1,761,000
6392267	Flash EPROM array with self-aligned source contacts and programmable sector erase architecture	Chitranjan N. Reddy	2002-05-21	$3,944,000
6373089	DRAM cell having storage capacitor contact self-aligned to bit lines and word lines	Chitranjan N. Reddy	2002-04-16	$4,846,000
6258714	Self-aligned contacts for salicided MOS devices	—	2001-07-10	$6,342,000
6166409	Flash EPROM memory cell having increased capacitive coupling	Perumal Ratnam	2000-12-26	$8,873,000
6133602	Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures	Chitranjan N. Reddy	2000-10-17	$13,189,000
6020237	Method of reducing dielectric damage due to charging in the fabrication of stacked gate structures	Chitranjan N. Reddy	2000-02-01	$12,556,000
5994730	DRAM cell having storage capacitor contact self-aligned to bit lines and word lines	Chitranjan N. Reddy	1999-11-30	$12,721,000
5856944	Self-converging over-erase repair method for flash EPROM	Bruce L. Prickett, Jr.	1999-01-05	$4,247,000
5731606	Reliable edge cell array design	Chitranjan N. Reddy	1998-03-24
5701264	Dynamic random access memory cell having increased capacitance	Chitranjan N. Reddy	1997-12-23	$2,996,000
5672535	Method of fabricating DRAM cell with self-aligned contact	C. Naveen Kumar Reddy	1997-09-30	$6,700,000
5557122	Semiconductor electrode having improved grain structure and oxide growth properties	Chitranjan N. Reddy	1996-09-17	$5,683,000
5518942	Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant	—	1996-05-21	$7,343,000
5416738	Single transistor flash EPROM cell and method of operation	—	1995-05-16	$16,396,000
4764248	Rapid thermal nitridized oxide locos process	Arya Bhattacherjee, William Koutny, Thurman J. Rodgers	1988-08-16	$4,976,000