Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10855261 | Level shifter with deterministic output during power-up sequence | James Nissen, David Wade Eickbusch | 2020-12-01 |
| 10453544 | Memory array with read only cells having multiple states and method of programming thereof | Brad J. Garni, Shayan Zhang | 2019-10-22 |
| 9899069 | Adaptable sense circuitry and method for read-only memory | — | 2018-02-20 |
| 9691495 | Memory array with RAM and embedded ROM | Scott I. Remington, Shayan Zhang | 2017-06-27 |
| 9317087 | Memory column drowsy control | Ravindraraj Ramaraju, Mark W. Jetton, Thomas W. Liston, George P. Hoekstra, Andrew C. Russell | 2016-04-19 |
| 9123545 | Semiconductor device with single-event latch-up prevention circuitry | James D. Burnett, Brad J. Garni, Thomas W. Liston | 2015-09-01 |
| 9026808 | Memory with word level power gating | Mark W. Jetton, Thomas W. Liston | 2015-05-05 |
| 8995178 | SRAM with embedded ROM | Brad J. Garni, Mark W. Jetton | 2015-03-31 |
| 8766703 | Method and apparatus for sensing on-chip characteristics | James D. Burnett, Mark W. Jetton, Thomas W. Liston | 2014-07-01 |
| 8685800 | Single event latch-up prevention techniques for a semiconductor device | James D. Burnett, Brad J. Garni, Thomas W. Liston, Huy Van Pham | 2014-04-01 |
| 8631292 | Multi-threading flip-flop circuit | Gary R. Morrison | 2014-01-14 |
| 8575962 | Integrated circuit having critical path voltage scaling and method therefor | Stephen G. Jamison, David L. Medlock, Gary Waugh | 2013-11-05 |
| 8446176 | Reconfigurable engineering change order base cell | Darrin L. Hutchinson, Stephen G. Jamison | 2013-05-21 |
| 7777522 | Clocked single power supply level shifter | Wang-Kun Chen, Stephen G. Jamison | 2010-08-17 |