| 11126438 |
System, apparatus and method for a hybrid reservation station for a processor |
Srikanth Srinivasan, Thomas Mullins, Ammon Christiansen, Robert S. Chappell, Sean P. Mirkes |
2021-09-21 |
| 10235180 |
Scheduler implementing dependency matrix having restricted entries |
Srikanth Srinivasan, Matthew C. Merten, Bambang Sutanto, Rahul Kulkarni, Justin M. Deinlein |
2019-03-19 |
| 9733939 |
Physical reference list for tracking physical register sharing |
Vijaykumar B. Kadgi, Avinash Sodani, Matthew C. Merten, Morris Marden, Joseph A. McMahon +4 more |
2017-08-15 |
| 9524191 |
Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elements |
Morris Marden, Matthew C. Merten, Alexandre J. Farcy, Avinash Sodani, Ilhyun Kim |
2016-12-20 |
| 9292288 |
Systems and methods for flag tracking in move elimination operations |
Vijaykumar B. Kadgi, Jeremy R. Anderson, Tong Li, Matthew C. Merten |
2016-03-22 |
| 9182986 |
Copy-on-write buffer for restoring program code from a speculative region to a non-speculative region |
Ravi Rajwar, David Sung-Eun Lim, Matthew C. Merten, Joseph A. McMahon, Yury N. Ilin +1 more |
2015-11-10 |
| 8521993 |
Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor |
Morris Marden, Matthew C. Merten, Alexandre J. Farcy, Avinash Sodani, Ilhyun Kim |
2013-08-27 |
| 8504804 |
Managing multiple threads in a single pipeline |
Matthew C. Merten, Avinash Sodani, Alexandre J. Farcy, Iredamola Olopade |
2013-08-06 |
| 8438369 |
Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor |
Morris Marden, Matthew C. Merten, Alexandre J. Farcy, Avinash Sodani, Ilhyun Kim |
2013-05-07 |
| 8402253 |
Managing multiple threads in a single pipeline |
Matthew C. Merten, Avinash Sodani, Alexandre J. Farcy, Iredamola Olopade |
2013-03-19 |
| 6931516 |
Pipelined instruction decoder for multi-threaded processors |
Jonathan P. Douglas, Daniel J. Deleganes |
2005-08-16 |
| 6609193 |
Method and apparatus for multi-thread pipelined instruction decoder |
Jonathan P. Douglas, Daniel J. Deleganes |
2003-08-19 |