Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11948069 | Compression of neural network activation data | Lingchuan Meng, John Brothers, Jens Olson, Jared C. Smolens, Eric Kunze | 2024-04-02 |
| 11449729 | Efficient convolutional neural networks | Lingchuan Meng, Danny D. Loh, Alexander Eugene Chalfin, Tianmu Li | 2022-09-20 |
| 11249908 | Technique for managing coherency when an agent is to enter a state in which its cache storage is unused | Ole Henrik Jahren, Sigurd Røed Scheistrøen | 2022-02-15 |
| 11188814 | Systolic convolutional neural network | Paul Nicholas Whatmough, Matthew Mattina | 2021-11-30 |
| 11170555 | Graphics processing systems | Andreas Due Engh-Halstvedt, Alexander Eugene Chalfin, Andreas Loeve Selvik, Olof Henrik Uhrenholt, Thomas J. Olson | 2021-11-09 |
| 11127110 | Data processing systems | Alexander Eugene Chalfin, Eric Kunze, Paul Stanley Hughes, Alex Kornienko, Damian Piotr Modrzyk +2 more | 2021-09-21 |
| 10956045 | Apparatus and method for issuing access requests to a memory controller | Andreas Hansson | 2021-03-23 |
| 10664399 | Filtering coherency protocol transactions | Hakan Persson, Andrew Brookfield Swaine, Bruce James Mathewson | 2020-05-26 |
| 10282338 | Configuring routing in mesh networks | Liewei Bao | 2019-05-07 |
| 10210092 | Managing cache access and streaming data | Chyi-Chang Miao, Christopher D. Metcalf, Carl Ramey | 2019-02-19 |
| 10157132 | Data processing systems using both a cache and a buffer for processing data | Edvard Fielding, Andreas Due Engh-Halstvedt, Jorn Nystad, Antonio Garcia Guirado, William Robert Stoye | 2018-12-18 |
| 10078589 | Enforcing data protection in an interconnect | Daniel Sara, Antony John Harris, Hakan Persson, Andrew Christopher Rose | 2018-09-18 |
| 10073778 | Caching in multicore and multiprocessor architectures | Anant Agarwal, Matthew Mattina | 2018-09-11 |
| 9514050 | Caching in multicore and multiprocessor architectures | Anant Agarwal, Matthew Mattina | 2016-12-06 |
| 9507745 | Low latency dynamic route selection | Carl Ramey, Matthew Mattina | 2016-11-29 |
| 9479431 | Route prediction in packet switched networks | Carl Ramey, Matthew Mattina | 2016-10-25 |
| 9384165 | Configuring routing in mesh networks | Liewei Bao | 2016-07-05 |
| 9304926 | Coherency control message flow | Mladen Wilder, Ole Henrik Jahren | 2016-04-05 |
| 9213652 | Managing cache access and streaming data | Chyi-Chang Miao, Christopher D. Metcalf, Carl Ramey | 2015-12-15 |
| 9135215 | Route prediction in packet switched networks | Carl Ramey, Matthew Mattina | 2015-09-15 |
| 8934347 | Low latency dynamic route selection | Carl Ramey, Matthew Mattina | 2015-01-13 |
| 8738860 | Computing in parallel processing environments | Patrick Robert Griffin, Mathew Hostetter, Anant Agarwal, Chyi-Chang Miao, Christopher D. Metcalf +15 more | 2014-05-27 |
| 8737392 | Configuring routing in mesh networks | Liewei Bao | 2014-05-27 |
| 8572353 | Condensed router headers with low latency output port calculation | Carl Ramey, Matthew Mattina | 2013-10-29 |
| 8560780 | Caching in multicore and multiprocessor architectures | Anant Agarwal, Matthew Mattina | 2013-10-15 |